Iam one among the many Verification Engineers based out of India
As there is enough material on ASIC flows /Testbenches /Scripting on the web, I would like to share few things on the evolving Verification methodology as UVM from my methodology experience/training sessions i attended !
As Iam also learning UVM , like to learn /explore more things by interacting with other guys , so feel free to post your comments . All the material posted here is to give a novice a basic idea about the methodology . Would like to add more references /examples/books/Q&A which can be of some help to everyone
Am reading a lot of blogs and thought would have one for myself!
This blog would contain more information on building test benches & on UVM!
During the course of time, I look forward to organise the content in a much better way
-Hash
As there is enough material on ASIC flows /Testbenches /Scripting on the web, I would like to share few things on the evolving Verification methodology as UVM from my methodology experience/training sessions i attended !
As Iam also learning UVM , like to learn /explore more things by interacting with other guys , so feel free to post your comments . All the material posted here is to give a novice a basic idea about the methodology . Would like to add more references /examples/books/Q&A which can be of some help to everyone
Am reading a lot of blogs and thought would have one for myself!
This blog would contain more information on building test benches & on UVM!
During the course of time, I look forward to organise the content in a much better way
-Hash
Good luck! Looking forward to your posts!
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