Dear Readers

While doing mock interviews this afternoon, came across this "what would be the difference between an object & component in UVM" ,thought of posting here



1) Objects are means of communication between components
2)Objects  can created and destroyed may times in over all simulation
3)Where as component are created only and once created they remain the same thou the simulation
4)Objects don't have phases and components have phases
5)Example of a component- all uvm components such as sequence item, sequencer.
6) Objects can be overridden and so can be the components by the factory
7) components have hierarchy and objects will not have hierarchy i.e the parent is agent is env, parent to env is test case

-Happy Reading

Hash

Dear Readers

Was going through UVM forums and came across this  "running a test" /tests per simulation",thought would add some more information and post it here.

Command line 

My_Simulator +UVM_TESTNAME=my_test1


Test:-

Lets understand about the test (my_test1 ) aka test scenario is a time consuming sequence in UVM ,could be a virtual sequence.An UVM test builds TB architecture , decides what sequence(s) are to be run ,end of test ,test pass/fail mechanism .There can be ONLY one test per simulation 

Lets understand "Test scenario can be possibly a virtual sequence".Let's assume the user has test1 that runs sequence1 and test2 that runs sequence2.

We  can create a higher level sequence (virtual sequence), and this sequence should start sequence1 and then start sequence2. Then  can have a single test that runs that virtual sequence.



This is  a case of sequence calling a sequence (nested sequences)?
b) If Yes, the test1 can be a single high level sequence(Virtual sequence) which can keep calling N sequences from within ?  This way , with a single test we can execute/cover all/most scenarios ?

Yes. There are several ways to do it.A sequence must run on a sequencer but it can be started by another sequence. A sequencer (virtual or not) is a structural uvm component which is created during build phase. A sequence (sequence_item) can be created any time.

So, in the original example, the virtual sequencer would have the handles to the original sequencer1 and sequencer2 for sequence1 and sequence2.. The virtual sequence can get those handles like: p_sequencer.sequencer1

-Happy Reading
Hash

Dear Readers

Lets talk again about the basic difference between Sequencers & Virtual Sequencers 

The basic difference between them is Virtual Sequencers are independent of protocol where as Sequencers are protocol /interface specific for that particular transaction

Thereby Virtual Sequencers control protocol /interface Sequencers and executes Virtual Sequences to control Protocol/Interface Sequences!

Hope you find it useful

-Happy Reading
Hash

Dear Readers

First let me Wish you all Happy festive days
Please feel free to email me with your suggestions/feedback and i am open for any constructive ideas which makes this small effort get better

We all know that UVM has the following simulation phase methods-Build time,run time & clean up 

UVM Simulation phase methods can be classified as build,connect, end of elaboration, start of simulation, run and clean up phases(extract, check,report)

Build ,connect, end of elaboration ,start of simulation, run, extract, check,report ,Final

Out of these phases ONLY build is the top down method and all others are bottom up methods ,all phase methods except RUN are functions and RUN is a  task.

So lets see what actually happens in each and every simulation phase method here 

During the build phase the factory is called and used to Construct various child components/ ports/exports and configured,the top level testbench topology is built 

During the connect phase the TLM connections are made and the ports/exports of the components are Connected. i.e, the environment topology is connected.

During the end of elaboration the connections are checked and used for configuring the components. Post elaboration activity and the topology is printed 

During the start of simulation the various files are opened  banner information /topology would be being printed (as below)

# ----------------------------------------------------------------

# UVM-1.0p1 

# (C) 2007-2011 Mentor Graphics Corporation

# (C) 2007-2011 Cadence Design Systems, Inc.

# (C) 2006-2011 Synopsys, Inc.

# ----------------------------------------------------------------

During the run phase main test is executed and simulation is run
UVM adds 12 new phases which would be executed in parallel  with run_phase
These 12 new phases would be used to control stimulus which is explained as below

pre_reset,
reset
post_reset
pre_config
config
post_config
pre_main
main
post_main
pre_shutdown
shutdown
post_shutdown

The stimulus control being done by the objection mechanism, lets see the codes

class my_test_phase extends uvm_test_phase;
//Factory registration
//Use component utils macro as its TB component
`uvm_component_utils(my_phase_test)
//Boiler Plate code which is mandatory for all UVM TB components
function new(string name ,uvm_component_parent)
super.new(name,parent);
//Boiler plate code end
endfunction

task ..._phase(uvm_phase phase)
phase.raise_objection(this, "Starting Phase");
//Sequence start
//end Sequence
phase.drop_objection(this, "Finished Phase");
endtask

endclass


Drivers and monitors would be using JUST this run_phase

During the extract, check, report,Final phase methods post processing is done and the required information /details are gathered on the final state of the DUT,results are checked for the extracted information and the test pass/fail reporting would be done.

One of the differences  between OVM and UVM is that there is no final phase method in ovm.

-Happy Reading
Hash

Dear Readers

Thought would post why the analysis port always uses new and NOT create?

The analysis port always uses  the same type of object and as it is not  a component and  does  not belong to the  factory hierarchy.

Ports are interfaces which  are not extending from either object or component, so we cannot use create and have to use new

-Happy Reading
Hash

Dear Readers

I was trying to understand where  polymorphism is used in UVM and i found this blogspot really interesting and its explained in detail with code examples

http://learn-verification.blogspot.in/2012/12/uvm-questions-3.html

Hope you also find it useful 

-Happy Reading
Hash

Dear Readers

I had a doubt on the uvm_do & uvm_do_with macros and this is what i understand from the UVM discussion forums and posting here as it may be useful for the interviews 

 uvm_do and uvm_do_with macros, the answer is that the second one assumes you need to further constrain your sequence/sequence_item(by providing this constraint as the second macro parameter) before it is get consumed. 

uvm_do does the following  3 things, 
1) create object 
2) object.randomize 
3) send packet 


 uvm_do_with there is only one difference, it calls 'randomize with ' (inline constraints) instead of randomize.

Hope you find it useful

-Happy Reading
Hash

Disclaimer

Posting on this blog to learn building UVM test benches, UVCs ,UVM VIPs from various online sources/discussion forums/Attended  training/Seminars /Webinars/Interviews. Am JUST sharing here to Learn from the experts and make this small effort better as i believe learning is a continuous process. Due credit goes to the trainers/online resources 

Dear Readers,

Came across this interesting topic on UVM discussion forums on linked in and posting on the blog as I found it real interesting! I JUST tried to organize the discussion to understand easily.

-Happy Reading

Hash

Topic: What are uvm_component_utils /uvm_object_utils and when to use these macros in UVM TB

As we all know that these uvm_component_utils /uvm_object_utils are the defined macros in UVM

There is a fundamental difference between objects and Components though both are classes that can be dynamically created while. Uvm_component is derived from uvm_object, and it adds the following:

1) Hierarchy management
2) Phasing
3) Reporting
4) configuration support
among other things.

Uvm_component -Should be used for objects that are of a "static" nature for the duration of the simulation

Uvm_object   should be used for other dynamically generated data, 

These macros are used for registering the type of uvm_component and uvm_object type objects respectively to the factory. So when you declare a class which is inherited from uvm_component, use uvm_component_utils and when you declare class inherited from uvm_object, use uvm_object_utils. 

They define uvm_component_registry and uvm_object_registry type proxy objects to register your own component/object types with factory. They are different because mechanism for creation of uvm_object and uvm_component type objects using the factory is different in UVM.

When to use uvm_component_utils /uvm_object_utils

On which factor the decision of using "uvm_component" or/either "uvm_object" depends.

 For eg. While creating "sequence" we use "uvm_seq_item" as base class & in this class we use "uvm_object_utils". Now let’s say in this case, if we use "uvm_component_utils" then what will be its impact.


Using either is not a choice, it’s more a must. One should have UVM class library hierarchy opened somewhere on the computer to see the type of the base class. If it is component then use uvm_component_utils, if object use the other one.


Use `uvm_component_utils for anything that is part of the UVM TB structure, including the top-level test that builds the rest of the TB.

Use `uvm_object_utils for anything that is data, such as your transaction class (extended from uvm_sequence_item) and any test sequences (extended from uvm_sequence).

You will not notice a difference until you try to create the components during the build phase or the data items during the runphase.

 If you declared the components or data with the wrong `_utils macro, you will get messages about the wrong number of formals or that there is no parent formal. Components have parents in the TB tree-structure while data is created as needed and does not have a parent. 

When we  build TB components i.e  Driver, Sequencer, Monitor, Agents, scoreboards , need to use uvm_component to register them, UVM provides individual parent classes for each of the components with in-built methods. so we just need to extend the class and build our  own components. 

UVM_objects is used for the things which are not part of the  TB structure i.e the stimulus. sequences use object, more clearly UVM_sequence and transaction class use UVM_Sequence items both directly derived from UVM_object. To keep the TB separate from the stimulus so that a test writer can alter its stimulus however he wanted a and the TB architecture remains unchanged. so it promotes more re-usability for the  TB

Disclaimer

Posting on this blog to learn building UVM test benches, UVCs ,UVM VIPs from various online sources/discussion forums/Attended  training/Seminars /Webinars/Interviews. Am JUST sharing here to Learn from the experts and make this small effort better as i believe learning is a continuous process. Due credit goes to the trainers/online resources 

To understand Sequencer -Sequence much better, i would like to add that sequencer is static and sequence is dynamic

Am working on creating UVC's at the moment and planning to share something soon.

-Hash

Some more information which may be useful

1)What is the difference between the Push/Pull interfaces in TLM communication

    with the Push interface control and data go in the same direction

    with the pull interface control and data go in the opposite direction

2)In the Sequence items do we randomize the input/output properties

In the Sequence item, we randomize the input properties which contain address/data

3) What does a clone do?

       A clone returns uvm_object

4)Advantage of Virtual interface

Through the Virtual interface classes connect to Physical pins in System Verilog

5)Analysis port & the difference between the regular ports

Analysis port is a regular port which supports broadcast mechanism
It can be connected to a single export /no export/multiple exports also called subscribers
Regular ports are 1:1 where as analysis port are 1:many or none

6)Sequences and the transactions are customizable via the factory pattern
  Sequences, Transactions,Sequence _items are dynamic and created at run time where as Sequencer/driver are static like components 

Dear Readers

Posting more information on UVM which would/may be useful for the interviews
Feel free to add any questions which may be helpful, this is  just a small effort from my side

-Happy Reading
Hash

1)Factory

uvm_factory is used to manufacture (create) UVM objects and components.

factory is a oops coding pattern

Allows test to change the type of a desired component or object

Typically set up at start of simulation

2)Virtual Interface

In SystemVerilog, a virtual interface is a handle variable that contains a reference to a static interface instance.

 Virtual interfaces allow the class-based portion of a verification environment to connect to physical interfaces containing signal definitions in the static module hierarchy.

3)Virtual Sequence

A sequence which controls stimulus generation across more than one sequencer, co-ordinate the stimulus across different interfaces and the interactions between them.

Usually the top level of the sequence hierarchy. AKA 'master sequence' or 'co-ordinator sequence'.

Virtual sequences do not need their own sequencer, as they do not link directly to drivers. When they have one it is called a virtual sequencer.

4)Virtual Sequencer

A virtual sequencer is a sequencer that is not connected to a driver itself, but contains handles for sequencers in the testbench hierarchy.

 It is an optional component for running of virtual sequences - optional because they need no driver hookup, instead calling other sequences which run on real sequencers.

5)Sequence

A class-based representation of one or more stimulus items (Sequence Items) which are executed on a driver.

Can collaborate in a hierarchy for successive abstraction of stimulus and can participate in constrained random setup to enable highly variable sets of stimulus above the randomization possible in an individual transaction.

Sequences can represent temporal succession of stimulus, or parallel tracks of competing or independent stimulus on more than one interface.

They can be built up into comprehensive stress test stimulus or real world stimulus particular to the needs of the protocol. UVM has comprehensive support the automated definition and application of sequences.

In its simplest form, a sequence is a function call (a functor), which may request permission to communicate with a driver using a sequence item.

 This complicated sounding interaction is not so complicated.

A sequence asks for permission to send a transaction (sequence item) to the driver.

Once it has been granted permission by the sequencer, then the transaction is passed to the driver.

6)Sequence Item

A class-based abstract transaction representing the lowest level of stimulus passed from a sequence to a driver. Also known as a Transaction.

7)Sequencer

A component responsible for co-ordinating the execution of stimulus in the form of sequences and sequence items from a parent sequence, ultimately feeding a driver component with transactions.

UVM/OVM provide a standard sequencer component with preset arbitration and locking methods for complex sequence stimulus.

 At its simplest, a sequencer can be thought of as s fancy arbiter.

 It arbitrates who gets access to the driver, which represents who gets access to the interface.

Sequence Item

 As UVM is based on classes it is a  class based transaction passed from the sequencer to the driver
 The lowest level of stimulus produced by the sequencer
This is also known as Transaction

Virtual Sequence

A sequence which controls stimulus generation across more than one sequencer, co-ordinate the stimulus across different interfaces and the interactions between them.
 Virtual sequences do not need their own sequencer, as they do not link directly to drivers.
 When they have one it is called a virtual sequencer.

Virtual Sequencer

A virtual sequencer is a sequencer that is not connected to a driver itself, but contains handles for sequencers in the test bench hierarchy.
It is an optional component for running of virtual sequences - optional because they need no driver hookup, instead calling other sequences which run on real sequencers.

Dear Readers

Please feel free to add any more information/comments which would help to make this attempt better

-Happy Reading
Hash


We can hearing about Virtual sequencer , what is the difference between the normal sequencer and the virtual sequencer?

 The difference between the normal & Virtual sequencer are  the sequence items apart from the Virtual keyword.
Virtual Sequencer  does not have its own sequence items , it just coordinates different sequencers and their sequences 

2)I was also asked why we need the create factory method when we already have new ()
  Am trying to find answer for this and would publish it once have more information

***************************************************************************

•  Factory is a OOPS coding pattern 
• Create() is a factory method which construct an object. 
• To override an object you need to construct it using create().
•  if you use set_type_override then before run ,factory replaces constructed object with derived object( specified in override). 
• If we use the  new() then you cant override the object.

******************************************************************************

3)In which UVM phases does the T/B components are created?


All the T/B components are compiled  initially ,but objects get created or newed during the build phase