Dear Readers,


One of our friends had some difficulty on "Testcase Parameters & Contents/Template of the test-case file"

Victor of Edaplayground.com has answered this query and due credit goes to Victor 

Lets understand how the  test case parameters can be driven inside the test bench environment  & the contents/template of the test case file?



In UVM, we typically use the uvm_config_db to parametrize the verification environment with methods like:
uvm_config_db#(string)::set
uvm_config_db#(string)::get

And +uvm_set_config_* options from the command line

References 


1)https://verificationacademy.com/verification-methodology-reference/uvm/docs_1.1d/html/files/base/uvm_cmdline_processor-svh.html#uvm_cmdline_processor.+uvm_set_config_int,+uvm_set_config_string

2)These  methods are used  in this UVM 1.2 example: 
http://www.edaplayground.com/s/4/1032


-Happy Reading
Hash

Dear Readers


Let us get started on how to build a UVM testbench given a DUT and timing diagrams in  a series of steps.
Take a dummy DUT as below.

Step-1

Lets  discuss the various components of a UVM testbench

  1)Sequencer              Class 
  2)Driver                    Class
  3)Scoreboard           Class
  4)Ports
  5)Virtual Interface
  6)Top Level module
  7)Interface
  8)Analysis Port
  9)Environment 

Step-2 

 Lets map all the components above in step-1 to UVM 
UVM testbench with all the mentioned components(Block diagram coming up)


Step-3

Lets look at a dummy DUT Pint out (Coming up soon)

Step-4 

Lets  have the timing diagrams for the dummy DUT (Coming up soon)

Step-5


Once we have a dummy DUT,timing diagrams and lets see how to build a UVM testbench 

Step-6

Lets list down the required files for the UVM testbench  as below

 1)Sequencer        i.e my_sequencer.sv                  (Class based)  
  2)Driver              i.e my_driver.sv                        (Class based)
  3)Scoreboard     i.e my_scoreboard.sv                (Class based)
  4)Top  module    i.e my_top.sv 
  5)Interface          i.e my_interface.sv
  6)Environment     i.e  my_env.sv
 7)Monitor            i.e my_monitor.sv  
   8)Sequence        i.e  my_sequence.sv
    9)Test               i.e my_test.sv       
  10)Agent            i.e  my_agent.sv
 11)Seq item         i.e  my_seq_item.sv
12)Config db        i.e  my_config_db.sv

Step-7

 Lets populate the codes for the files in step-6(Coming up soon)


-Happy Reading
Hash
    

Disclaimer

This is JUST to  give a basic understanding in terms of -Look & feel of UVM testbench-Various components-what all files we need to create for a UVM testbench and how to populate the files to get started. Its a small effort to create an UVM testbench given a DUT and timing diagram and the codes MAY NOT BE CLEAN COMPILE at the moment.

Dear Readers

Posting some more information which would be useful in creating a UVM test bench given any given DUT
We would see on how to build UVM T/B with the steps below very soon.
Hope you find this useful and feel free to share your comments!

-Happy Reading
Hash

Steps to build UVM T/B given any DUT:

1. Read the design

   - List down features
   - List down scenarios
   - Create test plan

2. Understanding DUT architecture

  - List down DUT interfaces
      o What kind of interface is it: ACTIVE or PASSIVE?
      o Active will require Driver and Scenario generator

3. Test bench architecture

 This would have the following components

  - DUT instantiated
  - All interfaces defined
  - UVC components instantiated (agents for each interface, ex: axi_master_agent or axi_slave_agent, etc)
  - Reference model mimicking the Design behaviour
  - Register layer model
  - Virtual sequencer which will instantiate all sequencers
  - Virtual sequences which will instantiate required sequences from different interfaces

4. Sequences

  They will be coded specific to each interface
  - Simple sequences like, write, read sequences
  - Sequences for configuring design registers

5. Test Library
  - Test case coded using virtual sequence

Disclaimer

   Posting on this blog to learn building UVM test benches, UVCs ,UVM VIPs from various online sources/Attended  training/Seminars /Webinars. Am JUST sharing here to Learn from the experts and make this small effort better as i believe learning is a continuous process. Due credit goes to the trainers/online resources.