Dear Readers

Lets  discuss few things about the task body of a sequence .We know that a sequence is made up of  N sequence items and has a task body() which differentiates a sequence from the sequencer code 

  Lets understand the what does the task body does 

1. It contains how many transactions would be sent to the driver
2 . It has to  create , randomize, start and finish the transactions.

Hope this is useful.Would post more code going forward.

-Happy Reading
Hash

Dear Readers,


Lets talk about the concept of verbosity in UVM, UVM_LOW,UVM_HIGH,UVM_MEDIUM

Lets try to understand this with an example - Think of UVM_LOW/MEDIUM/HIGH as stones of various sizes and take a basic sand filter. If we set the filter size as low , the stone which are  bigger than the size of the filter would not be through .
I.e if the  filter is set to MEDIUM the stones which are LOW/MEDIUM would be through the filter and HIGH would not be there .If we set the filter is set to HIGH then we can see the LOW/MEDIUM/HIGH would be  through.


If we apply the same concept to UVM and set the verbosity as UVM_MEDIUM  in the log file we can see the messages UVM_LOW,UVM_MEDIUM  and UVM_HIGH would be filtered out
The same way if we set the verbosity to UVM_HIGH everything LOW/HIGH/MEDIUM would be present in the log file  JUST think the filter as simulation filter

-Happy Reading
Hash

Dear Readers

 Lets discuss some more things about the factory pattern -Where we use/don't use factory pattern in the UVM test bench

1)To run the test by registering with the factory 
     If you want to run any test i.e my_test it should be registered with the factory pattern 
  
2)for all the UVM  test bench components

     UVM test bench components like driver/monitor/scoreboard/sequencer

3)For all the objects in the UVM test bench 
4)Not for the static connections 

As Factory is used for dynamic interconnections we can not use factory pattern for interfaces, coverage,cover groups,TLM ports/FIFOs

-Happy Reading
Hash

Dear Readers

Lets consider an  UVM TB (With a connected DUT)  with  the data(i.e the sequence items) flowing in and out of the DUT. This data  would be stored in the class based format which would be from uvm_sequence_item or uvm_sequence 

-Happy Reading
Hash

Dear Readers

One of our friends had a small confusion in build Phase of a UVM component.


Question:-   In some components the sub components  are initialized by “new()” function, sometimes the sub components  are initialized using “create()” method  inside build method.
So how to understand in what scenario this different ways is followed.


Victor Lyuboslavsky of edaplayground.com has explained it  nicely as below ,due credit goes to Victor

  
Using create() method does two things:

- register the component in the UVM hierarchy. create() must be used for structural components such as uvm_env, uvm_scoreboard, uvm_driver, etc.
- allow the code at a higher level (like at uvm_test) to override the type of component returned. It is a use of the Factory design pattern (https://en.wikipedia.org/wiki/Factory_design_pattern )

So, in short, only use new() if the component is not part of the UVM hierarchy (like a sequence item) AND you will never need to override that component with something else (like another subclass).


Hope you find this useful. All due credit to Victor Lyuboslavsky  ,thanks a lot Victor

-Happy Reading
Hash

Disclaimer : This is JUST a small place where i keep updating of small things i know of.
Am NO expert in UVM and  i learn from all possible resources  available and post it here for my OWN understanding.Due credit  goes to the resources/authors 

Dear Readers,

 protocol verification -some thoughts

For any protocol verification we can always generate a UVM TB
Lets see what all  minimum TB components  we should have - a  monitor  & interface signals for DUT Pins

A scoreboard is good if we want/need to  track the history/state of the protocol.
 A driver is only needed when the TB is ACTIVE -- if we  need to send responses on the bus or to create traffic.

Scenario-1

Lets think of a scenario  of no DUT & ONLY  "interface" for the pins of the DUT.
Is it possible to simulate UVM components without DUT?

 Yes.It is even possible to simulate your UVM components without the DUT. 

Please use the SV Unit framework to simulate a UVM driver:  

take a look http://www.edaplayground.com/s/example/205

-Happy Reading
Hash

Dear Readers

Lets discuss some more things about UVM agent.

• Agents can be either active or passive
• Agents provide all Verification logic for a DUT
• An active agent is driven on an interface/device with all Sequencer/driver/Monitor being available
• A passive agent has ONLY monitor available -Can do  checking & collect  coverage  
• Any Bus protocol can have N no of devices each of which is represented as an agent 
• An env has multiple agents which encapsulates and configures multiple agents, which is also known as UVC-Universal Verification component 
• Encapsulation this UVCs makes it modular and easy to maintain and Virtual sequences enable control at System Level

Happy Reading

Hash

Dear Readers


In UVM  we keep hearing these terms sequences/sequencer /transaction . lets try to understand these terms as below

-Happy Reading
Hash



Sequencer 

is a stimulus generator which returns random data item when requested by driver.
Sequencer  controls the flow of  sequences from sequencer to the driver

Using sequence we can add constraints to generate controlled randomized values of stimulus..
Transaction is the input to the DUT from driver component and transaction  is a set of sequences



Sequence {provides control on distribution of randomized values} ----> sequencer --(generates randomized stimulus when requested by Driver)----> transaction sent to DUT

 Sequences consist of randomized values of transactions i.e data items or sequence items
 Thus generated  sequences will be sent by the sequencer to the driver upon  request.
 Ultimately these transactions or data items, will be passed on to the DUT after the driver finishes its execution upon transactions.

The Sequences would be executed during the run phase

Sequence has the task_body() where as  the sequencer dont have it !
This is one of the many interview questions which i was asked on UVM.