Dear Readers

Posting more information on UVM which would/may be useful for the interviews
Feel free to add any questions which may be helpful, this is  just a small effort from my side

-Happy Reading
Hash

1)Factory

uvm_factory is used to manufacture (create) UVM objects and components.

factory is a oops coding pattern

Allows test to change the type of a desired component or object

Typically set up at start of simulation

2)Virtual Interface

In SystemVerilog, a virtual interface is a handle variable that contains a reference to a static interface instance.

 Virtual interfaces allow the class-based portion of a verification environment to connect to physical interfaces containing signal definitions in the static module hierarchy.

3)Virtual Sequence

A sequence which controls stimulus generation across more than one sequencer, co-ordinate the stimulus across different interfaces and the interactions between them.

Usually the top level of the sequence hierarchy. AKA 'master sequence' or 'co-ordinator sequence'.

Virtual sequences do not need their own sequencer, as they do not link directly to drivers. When they have one it is called a virtual sequencer.

4)Virtual Sequencer

A virtual sequencer is a sequencer that is not connected to a driver itself, but contains handles for sequencers in the testbench hierarchy.

 It is an optional component for running of virtual sequences - optional because they need no driver hookup, instead calling other sequences which run on real sequencers.

5)Sequence

A class-based representation of one or more stimulus items (Sequence Items) which are executed on a driver.

Can collaborate in a hierarchy for successive abstraction of stimulus and can participate in constrained random setup to enable highly variable sets of stimulus above the randomization possible in an individual transaction.

Sequences can represent temporal succession of stimulus, or parallel tracks of competing or independent stimulus on more than one interface.

They can be built up into comprehensive stress test stimulus or real world stimulus particular to the needs of the protocol. UVM has comprehensive support the automated definition and application of sequences.

In its simplest form, a sequence is a function call (a functor), which may request permission to communicate with a driver using a sequence item.

 This complicated sounding interaction is not so complicated.

A sequence asks for permission to send a transaction (sequence item) to the driver.

Once it has been granted permission by the sequencer, then the transaction is passed to the driver.

6)Sequence Item

A class-based abstract transaction representing the lowest level of stimulus passed from a sequence to a driver. Also known as a Transaction.

7)Sequencer

A component responsible for co-ordinating the execution of stimulus in the form of sequences and sequence items from a parent sequence, ultimately feeding a driver component with transactions.

UVM/OVM provide a standard sequencer component with preset arbitration and locking methods for complex sequence stimulus.

 At its simplest, a sequencer can be thought of as s fancy arbiter.

 It arbitrates who gets access to the driver, which represents who gets access to the interface.