Dear Readers

Thought of posting some code and here we go with the first program "hello world" and  have comments in the code to understand better .
 Please feel free to share your comments to make this small  effort better

-Hash

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 //Import the uvm_package
 import uvm_pkg::*;
`include "uvm_macros.svh"
program bhogadib;
       //uvm_component is the base class & my_test is the derived class
    class my_test extends uvm_component ;
              //utility macro to enable automation
             `uvm_component_utils(my_test)
            //Boilerplate code begin
            function new(string name,uvm_component parent);
            super.new(name,parent);
            endfunction
         //Boilerplate code end
    endclass
       initial begin
           //execute the UVM testcase
          run_test("my_test");
         uvm_report_info("Message","Hello world!!!!!");
        //Print what all types are available in the factory
       factory.print();
     //print the TB structure
    uvm_top.print_topology();
  end
endprogram

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# Loading sv_std.std
# Loading mtiUvm.uvm_pkg
# Loading work.first_uvm_test_sv_unit
# Loading work.bhogadib(fast)
# Loading C:\questa_sim_10.0b\uvm-1.0p1\win32\uvm_dpi.dll

# UVM_INFO @ 0: reporter [Message] Hello world!
#
#### Factory Configuration (*)
#
#   No instance or type overrides are registered with this factory
#
# All types registered with the factory: 37 total
# (types without type names will not be printed)
#
#   Type Name
#   ---------
#   my_test
# (*) Types with no associated type name will be printed as <unknown>
#
####
#
# UVM_INFO @ 0: reporter [UVMTOP] UVM testbench topology:
# ----------------------------------
# Name          Type     Size  Value
# ----------------------------------
# uvm_test_top  my_test  -     @455
# ----------------------------------
#
# 1
# Simulation stop requested.
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