Dear Readers

Posting some more information which would be useful in creating a UVM test bench given any given DUT
We would see on how to build UVM T/B with the steps below very soon.
Hope you find this useful and feel free to share your comments!

-Happy Reading
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Steps to build UVM T/B given any DUT:

1. Read the design

   - List down features
   - List down scenarios
   - Create test plan

2. Understanding DUT architecture

  - List down DUT interfaces
      o What kind of interface is it: ACTIVE or PASSIVE?
      o Active will require Driver and Scenario generator

3. Test bench architecture

 This would have the following components

  - DUT instantiated
  - All interfaces defined
  - UVC components instantiated (agents for each interface, ex: axi_master_agent or axi_slave_agent, etc)
  - Reference model mimicking the Design behaviour
  - Register layer model
  - Virtual sequencer which will instantiate all sequencers
  - Virtual sequences which will instantiate required sequences from different interfaces

4. Sequences

  They will be coded specific to each interface
  - Simple sequences like, write, read sequences
  - Sequences for configuring design registers

5. Test Library
  - Test case coded using virtual sequence

Disclaimer

   Posting on this blog to learn building UVM test benches, UVCs ,UVM VIPs from various online sources/Attended  training/Seminars /Webinars. Am JUST sharing here to Learn from the experts and make this small effort better as i believe learning is a continuous process. Due credit goes to the trainers/online resources.