Dear Readers


Let us get started on how to build a UVM testbench given a DUT and timing diagrams in  a series of steps.
Take a dummy DUT as below.

Step-1

Lets  discuss the various components of a UVM testbench

  1)Sequencer              Class 
  2)Driver                    Class
  3)Scoreboard           Class
  4)Ports
  5)Virtual Interface
  6)Top Level module
  7)Interface
  8)Analysis Port
  9)Environment 

Step-2 

 Lets map all the components above in step-1 to UVM 
UVM testbench with all the mentioned components(Block diagram coming up)


Step-3

Lets look at a dummy DUT Pint out (Coming up soon)

Step-4 

Lets  have the timing diagrams for the dummy DUT (Coming up soon)

Step-5


Once we have a dummy DUT,timing diagrams and lets see how to build a UVM testbench 

Step-6

Lets list down the required files for the UVM testbench  as below

 1)Sequencer        i.e my_sequencer.sv                  (Class based)  
  2)Driver              i.e my_driver.sv                        (Class based)
  3)Scoreboard     i.e my_scoreboard.sv                (Class based)
  4)Top  module    i.e my_top.sv 
  5)Interface          i.e my_interface.sv
  6)Environment     i.e  my_env.sv
 7)Monitor            i.e my_monitor.sv  
   8)Sequence        i.e  my_sequence.sv
    9)Test               i.e my_test.sv       
  10)Agent            i.e  my_agent.sv
 11)Seq item         i.e  my_seq_item.sv
12)Config db        i.e  my_config_db.sv

Step-7

 Lets populate the codes for the files in step-6(Coming up soon)


-Happy Reading
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Disclaimer

This is JUST to  give a basic understanding in terms of -Look & feel of UVM testbench-Various components-what all files we need to create for a UVM testbench and how to populate the files to get started. Its a small effort to create an UVM testbench given a DUT and timing diagram and the codes MAY NOT BE CLEAN COMPILE at the moment.