Dear Readers

Lets take a look at a simple  objection mechanism which can be used to control the end of test
We are using the same template which is used for the first program "Hello world" to keep it simple 

-Happy Reading
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*********************************************************************************
 program dummy_progrm;
 //Import the uvm_package
 import uvm_pkg::*;
`include "uvm_macros.svh"
class hello_world extends uvm_component;
//Factory registration
`uvm_component_utils(hello_world)
//Boiler plate code start
function new (string name,uvm_component parent);
super.new(name,parent);
endfunction
//Boiler plate code end 
virtual task run();
uvm_test_done.raise_objection(this);
uvm_report_info("Message","Hello World");
uvm_test_done.drop_objection(this);
global_stop_request();
//Print what all types are available in the factory
    factory.print();
    //Print the TB structure
   uvm_top.print_topology();
endtask
//standard phase methods
endclass
initial 
  begin
    run_test("hello_world");
      end
endprogram
*********************************************************************************

# Loading sv_std.std
# Loading mtiUvm.uvm_pkg
# Loading work.dummy_progrm(fast)
# Loading C:\questa_sim_10.0b\uvm-1.0p1\win32\uvm_dpi.dll
run
# ----------------------------------------------------------------
# UVM-1.0p1 
# (C) 2007-2011 Mentor Graphics Corporation
# (C) 2007-2011 Cadence Design Systems, Inc.
# (C) 2006-2011 Synopsys, Inc.
# ----------------------------------------------------------------
# UVM_INFO @ 0: reporter [RNTST] Running test hello_world...
# UVM_INFO @ 0: uvm_test_top [Message] Hello World
# 
#### Factory Configuration (*)
# 
#   No instance or type overrides are registered with this factory
# 
# All types registered with the factory: 37 total
# (types without type names will not be printed)
# 
#   Type Name
#   ---------
#   hello_world
# (*) Types with no associated type name will be printed as <unknown>
# 
####
# 
# UVM_INFO @ 0: reporter [UVMTOP] UVM testbench topology:
# --------------------------------------
# Name          Type         Size  Value
# --------------------------------------
# uvm_test_top  hello_world  -     @455 
# --------------------------------------
# 
# UVM_INFO verilog_src/uvm-1.0p1/src/base/uvm_objection.svh(1116) @ 0: reporter [TEST_DONE] 'run' phase is ready to proceed to the 'extract' phase
# 
# --- UVM Report Summary ---
# 
# ** Report counts by severity
# UVM_INFO :    4
# UVM_WARNING :    0
# UVM_ERROR :    0
# UVM_FATAL :    0
# ** Report counts by id
# [Message]     1
# [RNTST]     1
# [TEST_DONE]     1
# [UVMTOP]     1
# ** Note: $finish    : C:/questa_sim_10.0b/win32/../verilog_src/uvm-1.0p1/src/base/uvm_root.svh(392)
#    Time: 0 ns  Iteration: 187  Instance: /dummy_progrm
# 1
# Break at C:/questa_sim_10.0b/win32/../verilog_src/uvm-1.0p1/src/base/uvm_root.svh line 392