Dear Readers
Let us take a look at coding the following things one step at a time in a series of steps
Initially we would understand the basic template, populate the list of files (in step-1) with an example
-Happy Reading
Hash
Step1) List of files
Sequence item i.e my_simple_sequence_item.sv
Sequencer i.e my_simple_sequencer.sv
Driver i.e my_simple_driver.sv
Env i.e my_simple_env.sv
How to run the test i.e my_simple_program.sv
Step2)Templates
Lets take a look at the default templates for each of the above files
a)my_simple_sequence_item.sv
What does this my_simple_sequence_item contain- This would contain all signals ,constraints, transfers
a)Include uvm macros
b)As UVM is made of classes & libraries ,lets declare class my_simple_sequence_item which would be extended from uvm_sequence_item
********************************************************************************
//Include uvm macros
import uvm_pkg::*;
`include "uvm_macros.svh"
// Code begin line #1
class my_simple_sequence_item extends uvm_sequence_item;
//Factory registration
//Boiler plate code start
//Boiler plate code end
//Signals declaration
//constraints
//Code end
endclass : my_simple_sequence_item
*********************************************************************************
Step-3)Codes
a)my_simple_sequence_item.sv
********************************************************************************
//Include uvm macros
import uvm_pkg::*;
`include "uvm_macros.svh"
// Code begin line #1
class my_simple_sequence_item extends uvm_sequence_item;
rand bit [3:0] a,b;
rand bit [31:0] c[];
constraint valid {c.size inside {[2:50]};}
`uvm_object_utils_begin(my_simple_sequence_item)
`uvm_field_int(a,UVM_ALL_ON)
`uvm_field_int(b,UVM_ALL_ON)
`uvm_field_array_int(c,UVM_ALL_ON)
`uvm_object_utils_end
function new(string name = "my_simple_sequence_items");
super.new(name);
endfunction
//Factory registration
//Boiler plate code start
//Boiler plate code end
//Signals declaration
//constraints
//Code end
endclass : my_simple_sequence_item
*********************************************************************************
b)my_simple_sequencer.sv
*********************************************************************************
//`include "uvm_macros.svh"
import uvm_pkg::*;
class my_simple_sequencer extends uvm_sequencer #(my_simple_sequence_item);
`uvm_sequencer_utils(my_simple_sequencer)
function new(string name,uvm_component parent);
super.new(name,parent);
`uvm_update_sequence_lib_and_item(my_simple_sequence_item)
endfunction
endclass
c)my_simple_driver.sv
********************************************************************************
import uvm_pkg::*;
`include "uvm_macros.svh"
class my_simple_driver extends uvm_driver #(my_simple_sequence_item);
`uvm_component_utils(my_simple_driver)
function new(string name,uvm_component parent);
super.new(name,parent);
endfunction
virtual task run();
forever begin
seq_item_port.get_next_item(req);
uvm_report_info("Normal" , "This is a simple_driver item");
req.print();
seq_item_port.item_done();
end
endtask
endclass
d)my_simple_env.sv
********************************************************************************
import uvm_pkg::*;
`include "uvm_macros.svh"
class my_simple_env extends uvm_component;
my_simple_sequencer sequencer;
my_simple_driver driver;
`uvm_component_utils_begin(my_simple_env)
`uvm_field_object(sequencer,UVM_DEFAULT)
`uvm_field_object(driver,UVM_DEFAULT);
`uvm_component_utils_end
function new(string name,uvm_component parent);
super.new(name,parent);
endfunction
virtual function void build();
super.build();
sequencer = new("sequencer", this);
driver = new("driver",this);
endfunction
virtual function void connect();
super.connect();
driver.seq_item_port.connect(sequencer.seq_item_export);
endfunction
endclass
Disclaimer : This is just a small effort to learn UVM and all feedback is welcome
Let us take a look at coding the following things one step at a time in a series of steps
Initially we would understand the basic template, populate the list of files (in step-1) with an example
-Happy Reading
Hash
Step1) List of files
Sequence item i.e my_simple_sequence_item.sv
Sequencer i.e my_simple_sequencer.sv
Driver i.e my_simple_driver.sv
Env i.e my_simple_env.sv
How to run the test i.e my_simple_program.sv
Step2)Templates
Lets take a look at the default templates for each of the above files
a)my_simple_sequence_item.sv
What does this my_simple_sequence_item contain- This would contain all signals ,constraints, transfers
a)Include uvm macros
b)As UVM is made of classes & libraries ,lets declare class my_simple_sequence_item which would be extended from uvm_sequence_item
********************************************************************************
//Include uvm macros
import uvm_pkg::*;
`include "uvm_macros.svh"
// Code begin line #1
class my_simple_sequence_item extends uvm_sequence_item;
//Factory registration
//Boiler plate code start
//Boiler plate code end
//Signals declaration
//constraints
//Code end
endclass : my_simple_sequence_item
*********************************************************************************
Step-3)Codes
a)my_simple_sequence_item.sv
********************************************************************************
//Include uvm macros
import uvm_pkg::*;
`include "uvm_macros.svh"
// Code begin line #1
class my_simple_sequence_item extends uvm_sequence_item;
rand bit [3:0] a,b;
rand bit [31:0] c[];
constraint valid {c.size inside {[2:50]};}
`uvm_object_utils_begin(my_simple_sequence_item)
`uvm_field_int(a,UVM_ALL_ON)
`uvm_field_int(b,UVM_ALL_ON)
`uvm_field_array_int(c,UVM_ALL_ON)
`uvm_object_utils_end
function new(string name = "my_simple_sequence_items");
super.new(name);
endfunction
//Factory registration
//Boiler plate code start
//Boiler plate code end
//Signals declaration
//constraints
//Code end
endclass : my_simple_sequence_item
*********************************************************************************
b)my_simple_sequencer.sv
*********************************************************************************
//`include "uvm_macros.svh"
import uvm_pkg::*;
class my_simple_sequencer extends uvm_sequencer #(my_simple_sequence_item);
`uvm_sequencer_utils(my_simple_sequencer)
function new(string name,uvm_component parent);
super.new(name,parent);
`uvm_update_sequence_lib_and_item(my_simple_sequence_item)
endfunction
endclass
*********************************************************************************
c)my_simple_driver.sv
********************************************************************************
import uvm_pkg::*;
`include "uvm_macros.svh"
class my_simple_driver extends uvm_driver #(my_simple_sequence_item);
`uvm_component_utils(my_simple_driver)
function new(string name,uvm_component parent);
super.new(name,parent);
endfunction
virtual task run();
forever begin
seq_item_port.get_next_item(req);
uvm_report_info("Normal" , "This is a simple_driver item");
req.print();
seq_item_port.item_done();
end
endtask
endclass
********************************************************************************
d)my_simple_env.sv
********************************************************************************
import uvm_pkg::*;
`include "uvm_macros.svh"
class my_simple_env extends uvm_component;
my_simple_sequencer sequencer;
my_simple_driver driver;
`uvm_component_utils_begin(my_simple_env)
`uvm_field_object(sequencer,UVM_DEFAULT)
`uvm_field_object(driver,UVM_DEFAULT);
`uvm_component_utils_end
function new(string name,uvm_component parent);
super.new(name,parent);
endfunction
virtual function void build();
super.build();
sequencer = new("sequencer", this);
driver = new("driver",this);
endfunction
virtual function void connect();
super.connect();
driver.seq_item_port.connect(sequencer.seq_item_export);
endfunction
endclass
*********************************************************************************
e)my_simple_program.sv
********************************************************************************
`include "my_simple_sequence_item.sv"
`include "my_simple_sequencer.sv"
`include "my_simple_driver.sv"
`include "my_simple_env.sv"
program dummy_progrm;
//Import the uvm_package
import uvm_pkg::*;
`include "uvm_macros.svh"
class my_test extends uvm_component;
//Factory registration
`uvm_component_utils(my_test)
my_simple_env env;
//Boiler plate code start
function new (string name,uvm_component parent);
super.new(name,parent);
endfunction
function void build();
env=my_simple_env::type_id::create("env",this);
endfunction
//Boiler plate code end
virtual task run();
uvm_test_done.raise_objection(this);
uvm_report_info("Message","my_test");
uvm_top.print_topology();
uvm_test_done.drop_objection(this);
global_stop_request();
//Print what all types are available in the factory
factory.print();
//Print the TB structure
uvm_top.print_topology();
endtask
//standard phase methods
endclass
initial begin
uvm_default_printer = uvm_default_tree_printer;
fork
run_test("my_test");
#500 global_stop_request();
join
uvm_top.print_topology();
end
endprogram
*********************************************************************************
f)Log
*********************************************************************************
# ----------------------------------------------------------------
# UVM-1.1b
# (C) 2007-2012 Mentor Graphics Corporation
# (C) 2007-2012 Cadence Design Systems, Inc.
# (C) 2006-2012 Synopsys, Inc.
# (C) 2011-2012 Cypress Semiconductor Corp.
# ----------------------------------------------------------------
#
# *********** IMPORTANT RELEASE NOTES ************
#
# You are using a version of the UVM library that has been compiled
# with `UVM_NO_DEPRECATED undefined.
# See http://www.eda.org/svdb/view.php?id=3313 for more details.
#
# You are using a version of the UVM library that has been compiled
# with `UVM_OBJECT_MUST_HAVE_CONSTRUCTOR undefined.
# See http://www.eda.org/svdb/view.php?id=3770 for more details.
#
# (Specify +UVM_NO_RELNOTES to turn off this notice)
#
# UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(215) @ 0: reporter [Questa UVM] QUESTA_UVM-1.2
# UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(217) @ 0: reporter [Questa UVM] questa_uvm::init(+struct)
# UVM_INFO @ 0: reporter [RNTST] Running test my_test...
# UVM_WARNING verilog_src/uvm-1.1b/src/seq/uvm_sequencer_base.svh(1436) @ 0: uvm_test_top.env.sequencer [UVM_DEPRECATED] Registering sequence 'uvm_random_sequence' with sequencer 'uvm_test_top.env.sequencer' is deprecated.
# UVM_WARNING verilog_src/uvm-1.1b/src/seq/uvm_sequencer_base.svh(1436) @ 0: uvm_test_top.env.sequencer [UVM_DEPRECATED] Registering sequence 'uvm_exhaustive_sequence' with sequencer 'uvm_test_top.env.sequencer' is deprecated.
# UVM_WARNING verilog_src/uvm-1.1b/src/seq/uvm_sequencer_base.svh(1436) @ 0: uvm_test_top.env.sequencer [UVM_DEPRECATED] Registering sequence 'uvm_simple_sequence' with sequencer 'uvm_test_top.env.sequencer' is deprecated.
# UVM_INFO @ 0: uvm_test_top [Message] my_test
# ......................///////////////////////////////////////////////////////
# UVM_INFO @ 0: reporter [UVMTOP] UVM testbench topology:
# uvm_test_top: (my_test@503) {
# env: (my_simple_env@511) {
# driver: (my_simple_driver@643) {
# rsp_port: (uvm_analysis_port@660) @660
# sqr_pull_port: (uvm_seq_item_pull_port@651) @651
# }
# sequencer: (my_simple_sequencer@520) {
# rsp_export: (uvm_analysis_export@528) @528
# seq_item_export: (uvm_seq_item_pull_imp@634) @634
# arbitration_queue: -
# lock_queue: -
# num_last_reqs: 'd1
# num_last_rsps: 'd1
# }
# sequencer: (my_simple_sequencer@520) {
# rsp_export: (uvm_analysis_export@528) @528
# seq_item_export: (uvm_seq_item_pull_imp@634) @634
# arbitration_queue: -
# lock_queue: -
# num_last_reqs: 'd1
# num_last_rsps: 'd1
# }
# driver: (my_simple_driver@643) {
# rsp_port: (uvm_analysis_port@660) @660
# sqr_pull_port: (uvm_seq_item_pull_port@651) @651
# }
# }
# }
#
#
#### Factory Configuration (*)
#
# Instance Overrides:
#
# Requested Type Override Path Override Type
# ----------------- -------------------------------- -----------------------
# uvm_sequence_item uvm_test_top.env.sequencer*.item my_simple_sequence_item
#
# No type overrides are registered with this factory
#
# All types registered with the factory: 43 total
# (types without type names will not be printed)
#
# Type Name
# ---------
# my_simple_driver
# my_simple_env
# my_simple_sequence_item
# my_simple_sequencer
# my_test
# questa_uvm_recorder
# (*) Types with no associated type name will be printed as <unknown>
#
####
#
# UVM_INFO @ 0: reporter [UVMTOP] UVM testbench topology:
# uvm_test_top: (my_test@503) {
# env: (my_simple_env@511) {
# driver: (my_simple_driver@643) {
# rsp_port: (uvm_analysis_port@660) @660
# sqr_pull_port: (uvm_seq_item_pull_port@651) @651
# }
# sequencer: (my_simple_sequencer@520) {
# rsp_export: (uvm_analysis_export@528) @528
# seq_item_export: (uvm_seq_item_pull_imp@634) @634
# arbitration_queue: -
# lock_queue: -
# num_last_reqs: 'd1
# num_last_rsps: 'd1
# }
# sequencer: (my_simple_sequencer@520) {
# rsp_export: (uvm_analysis_export@528) @528
# seq_item_export: (uvm_seq_item_pull_imp@634) @634
# arbitration_queue: -
# lock_queue: -
# num_last_reqs: 'd1
# num_last_rsps: 'd1
# }
# driver: (my_simple_driver@643) {
# rsp_port: (uvm_analysis_port@660) @660
# sqr_pull_port: (uvm_seq_item_pull_port@651) @651
# }
# }
# }
#
# UVM_INFO verilog_src/uvm-1.1b/src/base/uvm_objection.svh(1120) @ 0: reporter [TEST_DONE] 'run' phase is ready to proceed to the 'extract' phase
#
# --- UVM Report Summary ---
#
# ** Report counts by severity
# UVM_INFO : 7
# UVM_WARNING : 3
# UVM_ERROR : 0
# UVM_FATAL : 0
# ** Report counts by id
# [Message] 1
# [Questa UVM] 2
# [RNTST] 1
# [TEST_DONE] 1
# [UVMTOP] 2
# [UVM_DEPRECATED] 3
# ** Note: $finish : C:/modeltech64_10.1c/win64/../verilog_src/uvm-1.1b/src/base/uvm_root.svh(408)
# Time: 0 ns Iteration: 184 Instance: /dummy_progrm
*********************************************************************************
f)Log
*********************************************************************************
# ----------------------------------------------------------------
# UVM-1.1b
# (C) 2007-2012 Mentor Graphics Corporation
# (C) 2007-2012 Cadence Design Systems, Inc.
# (C) 2006-2012 Synopsys, Inc.
# (C) 2011-2012 Cypress Semiconductor Corp.
# ----------------------------------------------------------------
#
# *********** IMPORTANT RELEASE NOTES ************
#
# You are using a version of the UVM library that has been compiled
# with `UVM_NO_DEPRECATED undefined.
# See http://www.eda.org/svdb/view.php?id=3313 for more details.
#
# You are using a version of the UVM library that has been compiled
# with `UVM_OBJECT_MUST_HAVE_CONSTRUCTOR undefined.
# See http://www.eda.org/svdb/view.php?id=3770 for more details.
#
# (Specify +UVM_NO_RELNOTES to turn off this notice)
#
# UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(215) @ 0: reporter [Questa UVM] QUESTA_UVM-1.2
# UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(217) @ 0: reporter [Questa UVM] questa_uvm::init(+struct)
# UVM_INFO @ 0: reporter [RNTST] Running test my_test...
# UVM_WARNING verilog_src/uvm-1.1b/src/seq/uvm_sequencer_base.svh(1436) @ 0: uvm_test_top.env.sequencer [UVM_DEPRECATED] Registering sequence 'uvm_random_sequence' with sequencer 'uvm_test_top.env.sequencer' is deprecated.
# UVM_WARNING verilog_src/uvm-1.1b/src/seq/uvm_sequencer_base.svh(1436) @ 0: uvm_test_top.env.sequencer [UVM_DEPRECATED] Registering sequence 'uvm_exhaustive_sequence' with sequencer 'uvm_test_top.env.sequencer' is deprecated.
# UVM_WARNING verilog_src/uvm-1.1b/src/seq/uvm_sequencer_base.svh(1436) @ 0: uvm_test_top.env.sequencer [UVM_DEPRECATED] Registering sequence 'uvm_simple_sequence' with sequencer 'uvm_test_top.env.sequencer' is deprecated.
# UVM_INFO @ 0: uvm_test_top [Message] my_test
# ......................///////////////////////////////////////////////////////
# UVM_INFO @ 0: reporter [UVMTOP] UVM testbench topology:
# uvm_test_top: (my_test@503) {
# env: (my_simple_env@511) {
# driver: (my_simple_driver@643) {
# rsp_port: (uvm_analysis_port@660) @660
# sqr_pull_port: (uvm_seq_item_pull_port@651) @651
# }
# sequencer: (my_simple_sequencer@520) {
# rsp_export: (uvm_analysis_export@528) @528
# seq_item_export: (uvm_seq_item_pull_imp@634) @634
# arbitration_queue: -
# lock_queue: -
# num_last_reqs: 'd1
# num_last_rsps: 'd1
# }
# sequencer: (my_simple_sequencer@520) {
# rsp_export: (uvm_analysis_export@528) @528
# seq_item_export: (uvm_seq_item_pull_imp@634) @634
# arbitration_queue: -
# lock_queue: -
# num_last_reqs: 'd1
# num_last_rsps: 'd1
# }
# driver: (my_simple_driver@643) {
# rsp_port: (uvm_analysis_port@660) @660
# sqr_pull_port: (uvm_seq_item_pull_port@651) @651
# }
# }
# }
#
#
#### Factory Configuration (*)
#
# Instance Overrides:
#
# Requested Type Override Path Override Type
# ----------------- -------------------------------- -----------------------
# uvm_sequence_item uvm_test_top.env.sequencer*.item my_simple_sequence_item
#
# No type overrides are registered with this factory
#
# All types registered with the factory: 43 total
# (types without type names will not be printed)
#
# Type Name
# ---------
# my_simple_driver
# my_simple_env
# my_simple_sequence_item
# my_simple_sequencer
# my_test
# questa_uvm_recorder
# (*) Types with no associated type name will be printed as <unknown>
#
####
#
# UVM_INFO @ 0: reporter [UVMTOP] UVM testbench topology:
# uvm_test_top: (my_test@503) {
# env: (my_simple_env@511) {
# driver: (my_simple_driver@643) {
# rsp_port: (uvm_analysis_port@660) @660
# sqr_pull_port: (uvm_seq_item_pull_port@651) @651
# }
# sequencer: (my_simple_sequencer@520) {
# rsp_export: (uvm_analysis_export@528) @528
# seq_item_export: (uvm_seq_item_pull_imp@634) @634
# arbitration_queue: -
# lock_queue: -
# num_last_reqs: 'd1
# num_last_rsps: 'd1
# }
# sequencer: (my_simple_sequencer@520) {
# rsp_export: (uvm_analysis_export@528) @528
# seq_item_export: (uvm_seq_item_pull_imp@634) @634
# arbitration_queue: -
# lock_queue: -
# num_last_reqs: 'd1
# num_last_rsps: 'd1
# }
# driver: (my_simple_driver@643) {
# rsp_port: (uvm_analysis_port@660) @660
# sqr_pull_port: (uvm_seq_item_pull_port@651) @651
# }
# }
# }
#
# UVM_INFO verilog_src/uvm-1.1b/src/base/uvm_objection.svh(1120) @ 0: reporter [TEST_DONE] 'run' phase is ready to proceed to the 'extract' phase
#
# --- UVM Report Summary ---
#
# ** Report counts by severity
# UVM_INFO : 7
# UVM_WARNING : 3
# UVM_ERROR : 0
# UVM_FATAL : 0
# ** Report counts by id
# [Message] 1
# [Questa UVM] 2
# [RNTST] 1
# [TEST_DONE] 1
# [UVMTOP] 2
# [UVM_DEPRECATED] 3
# ** Note: $finish : C:/modeltech64_10.1c/win64/../verilog_src/uvm-1.1b/src/base/uvm_root.svh(408)
# Time: 0 ns Iteration: 184 Instance: /dummy_progrm
*********************************************************************************
Disclaimer : This is just a small effort to learn UVM and all feedback is welcome
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