Dear Readers

Posting some questions from Doulos webinar here for anyone who have missed them 
Sure would be useful for interviews.Due credit goes to Doulos and i JUST posted them here

-Happy Reading
Hash


Audience Question:
Q: why do we use create instead of new ?
A: In order to be able to override the type of the object being created at run-time. This is what the factory does.


Audience Question:
Q: what do we mean when we say that we can modify the kind of object when using create method ?
A: Create one type of object instead of another, for example, replacing a transaction type with another transaction type that has additional properties or constraints

Audience Question:

Q: Can you plz explain how factory is linked with a class
A: With the factory pattern, instead of instantiating a new object by calling new, you call create (= the factory method). The type of the object being created by the factory can be overridden.

Audience Question:
Q: cant the instantiation of my_env be done in new constructor?
A: Yes it could, but that is not recommended practice. In UVM, component instantiation should always be done from the  build_phase method

Audience Question:
Q: but here we had m_env of type my_env
A: True. By settting a factory override, you could have create make an object of some other type (i.e. not my_env)

Audience Question:
Q: and we created the object of my_env type only..
A: No, not necessarily. That is the point of the factory.

Audience Question:
Q: did we overtride the type in this case ?
A: No, we have not actually seen any factory overrides, but they are very simple

Audience Question:
Q: What is the use of UVM_MEDIUM?
A: Sets the verbosity level of the information message, which can be used to filter out messages with "high verbosity". It's just a way of filtering the amount of information that gets reported

Audience Question:
Q: #10 is 10 units... what unit is it?
A: This just goes back to Verilog. It would be 10 "time units" as defined by the `timescale directive or time units statement.

Audience Question:
Q: What is the meaning of UVM_MEDIUM?what are the other things we pass in that place?
A: A verbosity level for this specific message. Not very important!

Audience Question:
Q: can the type of m_env be changed to other than my_env while doing create ?
A: A factory override can be set BEFORE calling create

Audience Question:
Q: What are the main difference between OVM and UVM ?
A: Replace "O" with "U". Literally! The first version of UVM was based on OVM 2.1.1, although UVM is now starting to diverge significantly from OVM. Unless you have OVM legacy code to maintain, you should focus on UVM.

Audience Question:
Q: can we consider UVM_MEDIUM as priority level?
A: No. It is just used to filter out information messages having "high verbosity", i.e. less important messages.

Audience Question:
Q: When to use UVM_MEDIUM?
A: You would only consider the verbosity level if you had a large number of information messages and wanted to filter out the less important ones.

Audience Question:
Q: dont we use program block to instantiate class
A: No. The program block was an early feature of SystemVerilog, closely tied to SystemVerilog's roots in OpenVera. You do not need to use a program block. In fact, you should NOT use a program block unless you really know exactly what you are doing and why you are doing it. If in doubt, use module instead.

Audience Question:
Q: Is the "my_test " is the test bebnch?
A: No, "my_test" is the test that we are going to run on the test bench


Audience Question:
Q: why we use drop_objection?
A: To bring the test to and end

Audience Question:
Q: What is the use of pkg?
A: A package is used for common, shared declarations, typically parameters, types, functions, tasks, and classes.


Audience Question:
Q: why run_test would take my_test (i.e a class) as an argument and not an instance of my_test ?
A: Good question. run_test uses the UVM factory to create the object of class my_test.



Audience Question:
Q: Suppose in my class I am not using `uvm_component_utils(class_name) but creating the same class object using create()  method. In this case can my class registerd in factory?
A: You would get a compile-time error! It is the uvm_component_utils macro that registers a class with the factory so that it  can be instantiated later by calling type_id::create()


Audience Question:
Q: The "my_test" in the model, is the test bench of the hello world design?
A: "my_test" is the test that runs on the test bench. In UVM, "test bench" and "verification environment" mean the same thing.Individual tests run on the test bench, perhaps by running specific sequences or adding constraints.

Audience Question:
Q: Which is the better way to pass clock? i mean from interface or from TOP ? Why?
A: Does not matter. The important thing is that the clock is generated from module-based code. An interface is being used here just to represent a bundle of wires. Depending on your design, there may or may not be clocks included in that bundle of wires. If you already have a clock generator in your module, you might want to pass the clock into the interface through a port on the interface.


Audience Question:
Q: why are we importing uvm_pkg inside DUT ?
A: To get access to names such as uvm_top and run_test, which are defined in the UVM library



Audience Question:
Q: When we change my_test, do we need to compile the entire testbench or only the my_test file?
A: Only the my_test file.


Audience Question:
Q: ideally we should not modify DUT .. right ?
A: Ideally we should be able to modify the tests, the verification environment, and the DUT independently of each other.



Audience Question:
Q: can you repeat virtual interface?
A: A virtual interface is in effect like a variable that contains a reference to an actual interface instantiation. It lets you refer to an interface instance from a class (in a package).


Audience Question:
Q: what is the use of config_db
A: The config_db is just a mechanism to parameterize the UVM component hierarchy.


Audience Question:
Q: List some important macros often used in building the environment?
A: `uvm_component_utils and `uvm_object_utils


Audience Question:
Q: what is difference between uvm_config_db and uvm_config_obj/int/string?
A: set_config_int/get_config_int were the methods used in OVM. These have been replaced by the uvm_config_db in UVM, although set/get_config_* still exist for backward compatibility


Audience Question:
Q: can we change get and set method parameter?? or we cant??
A: The answer will be "yes", whichever ;-)


Audience Question:
Q: What is the effect of scope in the configuration database
A: The scope corresponds to hierarchical path names in the UVM component hierarchy. In other words, the config_db allows  you to parameterize specific instances in the component hierarchy.


Audience Question:
Q: Is it neccesary to use config db to connect the driver to DUT ?
A: No, but it’s a good way to do it.


Audience Question:
Q: if you had to have multiple instance of driver with using different instance of the interface how will config db set and get work ?
A: The point of the config db is that it relates to the UVM component hierarchy. So you can set a different virtual interface for each driver instance.


Audience Question:
Q: If i have more tests and i want to simulate all at a time , is it possible?? if yes how?
A: You could write one mega-test that runs all the others, or you could use a script to run several tests (sequentially or  concurrently on a server farm)


Audience Question:
Q: is there any better feature db provides over ovm's set/get functions/
A: uvm_config_db is better than OVM's set/get_config_* in the sense that the uvm_config_db supports ANY data type, and is not restricted to int/string/ovm_object


Audience Question:
Q: when to use `uvm_component_utils and `uvm_object_utils?
A: `uvm_component_utils for components, `uvm_object_utils for transactions and sequences

Audience Question:
Q: when to use resource_db and config_db?
A: uvm_config_db uses uvm_resource_db. You don't NEED to use uvm_resource_db directly, but you can if you like. With uvm_resource_db, the scope of each parameter is NOT necessarily related to the UVM component hierarchy.


Audience Question:
Q: In set and get the argument in quotes should remain same right?
A: Each item has a scope, a name, and a value. It you want to set a given parameter and then get it out again, the scope and name have to match.


Audience Question:
Q: can i use fork and join to run all test at a time?? or it is not proper way to do that??
A: If you fork/join a bunch of tests, all the tests will be trying to run at the same time on the same verification environment, so would just collide with each other. So you would either run them in series, or run them in parallel as different simulations.


Audience Question:
Q: can we collect coverage in uvm without monitor?
A: You can collect coverage wherever you like. In UVM, the issue to think about is always re-use. So you could collect lowlevel coverage data in a monitor, but you would want to collect test-specific data from some higher-layer component


Audience Question:
Q: In my_test, which will be better way1) eisther use sart item... finish item or as you mention in mytest
A: start_item and finish_item can ONLY be called from within a sequence. From a test, you would call
sequence.start(sequencer).


Audience Question:
Q: what is use of get_config Is there any functionality behind that?
A: get_config_* has been replace by uvm_config_db#(T)::get() in UVM.


Audience Question:
Q: what is the function of driver and monitor?
A: A driver wiggles pins, a monitor senses pin wiggles.


Audience Question:
Q: Can we have many sequences and one sequencer to drive data to driver in my environment?
A: Yes. As many as you need.

Audience Question:
Q: what is the function of driver and monitor?
A: A driver wiggles pins, a monitor senses pin wiggles.

Audience Question:
Q: why we always use analysis port in monitor?? what if i use simple port or export??
A: An analysis port allows the same transaction to be broadcast to multiple components or to none. Regular (non-analysis) ports have to be connected to a single export.


Audience Question:
Q: do_copy() methos is shallow copy or deep copy?
A: You can write it to do whatever you want
.
Audience Question:
Q: How do i Run multipla testcases in one Mega test case which includes all the testcases in need to runn?
A: You write the megatest to do whatever you want to do. But what is the issue? If you want to run multiple tests, you would generally do better to create a script or use some kind of test management tool.


Audience Question:
Q: Believe the copy is a shallow copy
A: When you override do_copy, you do whatever you want to do. The idea is that you can make the copy/compare/etc just as deep or shallow as you need.

Audience Question:
Q: In the do_copy() method, $cast is used, but there is no constructor used
A: Yes, that is how it works.


Audience Question:
Q: what are differnce between OVM and UVM?
A: Replace "O" with "U". Literally! The first version of UVM was based on OVM 2.1.1, although UVM is now starting to diverge significantly from OVM. Unless you have OVM legacy code to maintain, you should focus on UVM.


Audience Question:
Q: why we derive sequence_iteam class form uvm_sequence_iteam() class not from uvm_component() ?
A: A sequence item is nothing like a component. A sequence item is dynamic, created on-the-fly during simulation. A component is quasi-static, created during the build_phase at the start of simulation, and linked into the UVM component  hierarchy.


Audience Question:
Q: In my env, uvm_error/info/warn is not working what could be the issue?
A: Give me another clue. Perhaps you have not raised any objections, so the test has stopped at time zero?

Audience Question:
Q: what is virtual interface?
A: A reference to an interface


Audience Question:
Q: each sequnce generates 8 transactions.. is it right ?
A: Right.


Audience Question:
Q: when is the starting_phase is set? at what time?
A: Before starting the sequence, e.g. from the test


Audience Question:
Q: In addition to my previous question, within the do_copy() method only a handle of transaction was created and no constructor was called. Does $cast implicity calls new() ?
A: Yes.


Audience Question:
Q: can 1 sequnce get bby 2 different driver?
A: You would usually want a different sequencer for each driver. The driver has a port than needs to be connected to the export of a sequencer from which it pulls down transactions.


Audience Question:
Q: Does send_request of OVM doesn't work in UVM?
A: There a lots of API methods in OVM and UVM, but best practice is to keep with a few specific coding styles as shown on these slides


Audience Question:
Q: why is he using if(!seq.randomize()) and not assert(seq.randomize())
A: You could use assert (seq.randomize()). The argument against doing so is that some simulators allow you to switch off  assertions, in which case the randomization would get removed


Audience Question:
Q: what do you mean by this -each sequnce generates 8 transactions.
A: Each time you start this sequence is generates 8 transactions (because it contains repeat(8))


Audience Question:
Q: seq.starting_phase=phase .... Is this statement compulsory ...?
A: Not compulsory. What is does is to set the starting_phase property of the sequence object, so that the sequence itself can raise and drop objections.


Audience Question:
Q: in my_sequence before randomising we need to start req or need to randomise and then start the req
A: start_item(req); req.randomize(); finish_item(req);

Audience Question:
Q: Can a Master Sequncer call N no of other sequnces?
A: Yes. There are several different approaches. Sequences can be nested, layered, or virtual ... (long story)


Audience Question:
Q: what are APIs and DPIs?
A: API = application programming interface. DPI = direct programming interface (lets you call C from SV)


Audience Question:
Q: Master Sequence can call N no of Other sequences?
A: Yes. There are several different approaches. Sequences can be nested, layered, or virtual ... (long story)


Audience Question:
Q: How can we handle registers and memories using UVM? Can you recommend me some sources of it (books, URLs, etc...)?
A: Well, there is the UVM register layer, aka uvm_reg. Check that out.


Audience Question:
Q: Is there any way to increase the no of sequences other than repeat?
A: This is just procedural code. sequence.start() runs a sequence. Call it whenever you like (from a test or another  sequence)

Audience Question:
Q: how can I keep updated for these seminars ?
A: By registering for this webinar, we will make sure you are kept up-to-date with future presentations.

Audience Question:
Q: how can i do nesting of sequences?
A: Nesting is easy. You can start a sequence from the body task of another sequence. Just create the sequence object (using the factory), randomize it, then call sequence.start()

Audience Question:
Q: Where exactly we need to use objections?
A: Objections are the mechanism used in UVM to bring tests to an end. The test (strictly, the phase) ends when the number of objections raised = 0.


Audience Question:
Q: Is there any way to nest sequences?
A: Nesting is easy. You can start a sequence from the body task of another sequence. Just create the sequence object (using the factory), randomize it, then call sequence.start()


Audience Question:
Q: How is uvm virtual interface different from system Verilog?
A: No. A virtual interface is System Verilog.

Audience Question:
Q: Why TLM - import and export features for driver and sequencer?
A: TLM is the usual way to connect components in the UVM verification environment. The sequencer and driver components are designed to communicate using TLM. That's how it is.

Audience Question:
Q: Any pointers to RAL in UVM ...?
A: The UVM register layer is known as uvm_reg.

Audience Question:
Q: how uvm virtual interface is different from system verilog?
A: It isn't. A virtual interface is SystemVerilog


Audience Question:
Q: could u pl.. explain factory registration
A: Nothing much to explain. The macros register the component/transaction/sequence with the factory so that the object can subsequently be instantiated by calling type_id::create()


Audience Question:
Q: y cant objection mechanism be default in UVM
A: The objection mechanism is the default in UVM. In other words, a UVM phase will end at time = zero if there are no objections raised. Any process that is "busy" needs to raise an objection (unless driven by something else)


Audience Question:
Q: What is the use of following statement "sequence.starting_phase=phase" in sequence body task?
A: Just sets the starting_phase property of the sequence object so the sequence can raise objections


Audience Question:
Q: in most of the test becnhes, we need to have register model, so please explain with one example
A: There is an example of uvm_reg in the source files that we have given you to download.


Audience Question:
Q: how to connect a reference implementation of the DUT as checker? Can the sequencer transmitt the transactions to 2  interfaces (Ref, DUT) the same time?
A: Yes, but the recommended approach would be to have a monitor (connected to the DUT pins) send the same transaction to a reference model (to calculate expected output from actual input) and checker (to compare expected output with actual output)


Audience Question:
Q: where can i get virtual interfaces concepts in terms of UVM?
A: A virtual interface is, in effect, like a variable that contains a reference to an interface instance. This is a SystemVerilog concept, not part of UVM as such

Audience Question:
Q: Driver uses pull-down method to get sequences.....There is a push method .. when is it used?
A: The usual way is with a pull interface. There is a push interface between driver and sequencer, but it is not much used.

Audience Question:
Q: what are APIs?
A: Application Programming Interface

Audience Question:
Q: Is there UVM for SystemC?
A: There are various partial implementations. For example, Cadence has one (UVM-SC) as part of their UVM-ML (mixed language)

Audience Question:
Q: Hi....Why do we require sequencer as a separate class? Can't it merged with Driver?
A: No, that would be bad practice. It is ALL ABOUT REUSE. That is the point of UVM

Audience Question:
Q: if we do not use objection mechanism .. will that be okay ? why it is must to use ?
A: You must use the objection mechanism (unless you are porting legacy OVM code into UVM)

Audience Question:
Q: could u please expalin reg model with example?
A: There is an example as part of the examples you will download. But you will NOT learn the register layer from one example. You need a training class!


Audience Question:
Q: here is looks like module is the highest in the hirarchy and then test and env and agent components .. is that correct conclusion ?
A: There is more than one hierarchy. In SystemVerilog there is always at least one top-level module, by definition. But there is also the UVM component hierarchy (an object hierarchy) and the UVM class hierarchy. It gets complicated ;-)


Audience Question:
Q: where the constraints for a transaction should be written? In testcase?
A: Several options. In a transaction class, or as in-line constraints in a test, or as in-line constraints in a sequence.


Audience Question:
Q: how to connect a reference implementation of the DUT as checker? Can the sequencer transmitt the transactions to 2 interfaces (Ref, DUT) the same time?
A: Yes, but the recommended approach would be to have a monitor (connected to the DUT pins) send the same transaction to a reference model (to calculate expected output from actual input) and checker (to compare expected output with actual output)


Audience Question:
Q: If we have a top-level sequence,which has references to 2-other sequences - seq1, seq2(the 2-sequences have a `uvm_do_with within their body task), so in the body() of the top-level seq - when we do a `uvm_do(seq1)- i assume this calls uvm_do of actual-seq1- so are the constraints in seq1- still valid in top-seq ?
A: Yes.


Audience Question:
Q: Is it needed to randomize the user defined variables at driver, sequencer, and test classes seperately to generate the random stimulus ?
A: Wherever you have an object that contains rand variables, you need to call object.randomize() to randomize the object. So "yes".


Audience Question:
Q: in which file, rtl signals and tb signals can be connected? is it in top file?
A: "tb signals" will be variables within a SystemVerilog interface. You would connect these to the DUT in a module instance.All of this will be module-based SV code. It does not have to be at the top level of the module hierarchy, though in most cases it would probably occur quite near the top of the module hierarchy.


Audience Question:
Q: For objection mechanisam ... if it is compulsory to do always in run_phase ... why is it not done in UVM base class itself .... thus avoiding user to do it eachtime? Or is there any application where we have run phase \wo objection mechanism
A: The UVM base class itself has no knowledge of your test or when it will be finished. You are asking from something that is actually very complicated and application-specific (i.e. when is the test done?) to appear very simple.

Audience Question:
Q: what is use of the finish_on_completion? Where exactly we need to call this?
A: Setting finish_on_completion=1 causes the UVM class library to call $finish at the end of the test (after all objections are dropped and phases complete).


Audience Question:
Q: here it looks like module is the highest in the hirarchy and then test and env and agent components .. is that correct conclusion ?
A: There is more than one hierarchy. In SystemVerilog there is always at least one top-level module, by definition. But there is also the UVM component hierarchy (an object hierarchy) and the UVM class hierarchy. It gets complicated ;-)

Audience Question:
Q: If we do not use objection mechanism .. will that be okay ? why is that must to use ?
A: If you do not use the objection mechanism, simulation will end at time zero. (The only exception is if you are trying to run legacy OVM code)


Audience Question:
Q: virtual interface is a pointer to physical interface ie su interface
A: In effect, yes.
Audience Question:
Q: what is the symbol for and operator in sv
A: & (bitwise and) or && (logical and)


Audience Question:
Q: what is the difference between pre_randomization() and post_randomization() concepts?
A: These are user-defined methods of a class that get called immediately before and immediately after and rand properties get randomized/solved.


Audience Question:
Q: why do we need clocking block in sv? and is it mandatory to use or optional?
A: Clocking blocks are never mandatory. But there are an excellent way to simplify the synchronization between the DUT and the verification environment in the case of synchronous DUT interface, so are strongly recommended.

Audience Question:
Q: What is the purpose of scoreboard , as a checker???
A: Usually, yes.

Audience Question:
Q: why is clock always generated in module based and not in class ?
A: Because otherwise it will totallly screw up the SystemVerilog scheduler.

Audience Question:
Q: How can you reuse a driver if it's necessary to get a interface by a specific name, which was given in the environment?
A: Good question. To avoid having this dependency, you could have some higher level UVM component (e.g. the test or the env) retrieve the parameter from the config_db by name and then set the virtual interface in the driver (which it "knows about").

Audience Question:
Q: Is there mechanish in UVM with that we can send txns to scorebord after some latency other that clock
A: Yes, you can delay transactions in the monitor as long as you like (if that is really what you want - but why not send the transactions immediatelhy and queue them in the scoreboard?)

Audience Question:
Q: if a var say 'x' is defined as rand, and it has been assigned a value before calling the `uvm_do(req)- will the var-'x' be randomized or would it have the value that has been assigned previously before the `uvm_do ?
A: If a variable is declared as rand, than obj.randomize() will randomize it unless you have called rand_mode(0)

Audience Question:
Q: Is it possible wiggle the DUT INPUT pins directly from the test class without using the sequence, transactions and driver ? Like using backdoor register access in register model ?
A: Yes, but really bad practice from the point of view of reuse.

Audience Question:
Q: u said (The only exception is if you are trying to run legacy OVM code) how will it know that a legacy code is being executed and it should not run out in zero sim time
A: You have to set a standard UVM command line flag +UVM_USE_OVM_RUN_SEMANTIC


Audience Question:
Q: what is type_id while creating components inuvm ?
A: It is a proxy class. You do not need to understand all the technical details to use it. But don't forget it!


Audience Question:
Q: Where we can put extra logic for verifying the DUT for ex start of frame, octet counter and others...
A: You would do low-level protocol checks like this either using SystemVerilog Assertions (necessarily in a module or interface) or in the monitor.

Audience Question:
Q: when to use set config and get config?
A: Don't! Use uvm_config_db#(T)::set/get to set and get parameters from the configuration database in order to parameterize your UVM component hierarchy

Audience Question:
Q: what is modport and why we use it in interfaces ?
A: Honestly, if you don't know what a modport is, you are best to forget it. You do not need to use modports at all. They simple act as filters between the contents of an SV interface and whatever is trying to access the contents of the SV interface from outside.

Audience Question:
Q: why are we using clocking block in the interface ... instead of it cant we use multiple interfaces with different clocks as its input ?
A: Clocking blocks are an excellent way to simplify the handling of synchronization issues between the DUT and the verification environment.

Audience Question:
Q: how can one implicitly fire sequences ?
A: I would strongly recommend that you don't even consider doing so until you have a good understanding of UVM. But if you really want to, you can set the "default_sequence" property of the sequencer.

Audience Question:
Q: why we are using extern keyword .. is it not possible without it ? what does exactly makes difference when we declare with extern keyword and without extern keyword ?
A: The extern keyword simply indicates that the task or function is defined textually outside of the class: the class merely contains the task/function name and arguments.

Audience Question:
Q: why do we need raise_objection and drop_objection constructs?
A: To control the end-of-test, i.e. when all the various elements of the verification environment have finished doing whatever they are doing.

Audience Question:
Q: what is mechanism provided to communicate betweendriver and monitor components?
A: It is best practice NEVER to communicate directly between driver and monitor components. Rather, the driver wiggles the pins of the DUT, and the monitor passively senses these pin wiggles.


Audience Question:
Q: Would you then get the virtual interface in the driver again using the config_db or passing the virtual interface by method call?
A: You could use the config_db, or the test/env could poke the value directly into the local virtual inteface using a hierachical object name, e.g. m_env.m_agent.m_driver.m_virtual_if = irtual_if_read_from_config_db;

Audience Question:
Q: In any situation can driver connect with monitor other than wiggling the pins of DUT?
A: This would usually be bad practice, but yes, sure, it would be very easy to do if you wanted to using any of the many
communication mechanisms in UVM

Audience Question:
Q: suppose din to DUT takes 10 clocks latency so I am sending txns to scoreboard after 10 clocks and ten checking txn v/s DUT  but how to make them queue in the SB plz let me know..
A: Just literally put a queue in the scoreboard.

Audience Question:
Q: how to take care of setup and hold time in sv uvm tb
A: This is really nothing to do with UVM. Just put these low-level timing details in the SystemVerilog interface.

Audience Question:
Q: usage of clocking blocks are mandatory in interface file
A: No, they are not mandatory


Audience Question:
Q: Which componenets are blocking /nonblocking and why?
A: The concept of blocking/non-blocking applies to method calls, not components. A blocking method is not guaranteed to return immediately, a non-blocking method is.

Audience Question:
Q: The extern keyword simply indicates that the task or function is defined textually outside of the class. The class merely contains the task/function name and arguments. So here the question is .. is it not possible to override or overlap the definition without extern function ?
A: The use of extern is entirly unrelated to whether or not you can override a method. It is purely syntactical. WIthout extern,the entire text of the method is written inside the class.

Audience Question:
Q: can i wait for triggering of event in test when event has been triggered in top module
A: Yes, but that does not sound like the right way to be thinking about things.

Audience Question:
Q: Can RALF file with register descriptions and hdl_path constructs used for a VMM register can be used to create UVM re
A: Synopsys do provide a version of ralgen that works with UVM.


Audience Question:
Q: So the always mentioned scoreboard is in fact a checker, or even THE checker. Correct?
A: The word "scoreboard" means whatever you want it to mean in UVM. Scoreboards typically do checking and coverage
collection.