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Friday 4 July 2014

Dear Readers

Lets  discuss few things about the task body of a sequence .We know that a sequence is made up of  N sequence items and has a task body() which differentiates a sequence from the sequencer code 

  Lets understand the what does the task body does 

1. It contains how many transactions would be sent to the driver
2 . It has to  create , randomize, start and finish the transactions.

Hope this is useful.Would post more code going forward.

-Happy Reading
Hash



Wednesday 21 May 2014

Dear Readers,


Lets talk about the concept of verbosity in UVM, UVM_LOW,UVM_HIGH,UVM_MEDIUM

Lets try to understand this with an example - Think of UVM_LOW/MEDIUM/HIGH as stones of various sizes and take a basic sand filter. If we set the filter size as low , the stone which are  bigger than the size of the filter would not be through .
I.e if the  filter is set to MEDIUM the stones which are LOW/MEDIUM would be through the filter and HIGH would not be there .If we set the filter is set to HIGH then we can see the LOW/MEDIUM/HIGH would be  through.


If we apply the same concept to UVM and set the verbosity as UVM_MEDIUM  in the log file we can see the messages UVM_LOW,UVM_MEDIUM  and UVM_HIGH would be filtered out
The same way if we set the verbosity to UVM_HIGH everything LOW/HIGH/MEDIUM would be present in the log file  JUST think the filter as simulation filter

-Happy Reading
Hash

Sunday 11 May 2014

Dear Readers

While doing mock interviews this afternoon, came across this "what would be the difference between an object & component in UVM" ,thought of posting here



1) Objects are means of communication between components
2)Objects  can created and destroyed may times in over all simulation
3)Where as component are created only and once created they remain the same thou the simulation
4)Objects don't have phases and components have phases
5)Example of a component- all uvm components such as sequence item, sequencer.
6) Objects can be overridden and so can be the components by the factory
7) components have hierarchy and objects will not have hierarchy i.e the parent is agent is env, parent to env is test case


-Happy Reading
Hash

Friday 9 May 2014

Dear Readers

 Found out these technical tutorials on UVM very interesting,take a look @ http://videos.accellera.org/uvmnownext/uvm349db45sh/index.html

Hope you find it good

-Happy Learning
Hash



Dear Readers

 JUST posting a discussion  on "differences between UVM Transaction & an UVM object from Verification academy. As it is well answered in the forum  lets directly refer to the thread and let i find it  good  https://verificationacademy.com/forums/uvm/difference-between-uvm-transaction-and-uvm-object

Hope you find it useful

-Happy Reading
Hash

Wednesday 7 May 2014

Dear Readers

One of our friends has a question about special ports( below) in UVM and how these ports are used in communication and what type of applications we may require this kind of ports.


uvm_blocking_put_imp_decl
uvm_blocking_master_imp_decl
`uvm_master_imp_decl etc...

As we know in UVM communication between the various components is by connecting ports to the suitable exports .

These special ports (above) are different variations of TLM API and can find more about these special ports on https://verificationacademy.com/verification-methodology-reference/uvm/docs_1.1d/html/files/tlm1/uvm_tlm_ifs-svh.html


Due credit goes to Victor Lyuboslavsky for answering this 

-Happy Reading
Hash

Dear Readers

 One of our friends has a question on Custom Phases of UVM. Would try to post as much information (i have) on this and would keep updating this post.

As we all know that UVM phases build,connect, end of elaboration, start of simulation,run, extract, check and report.

 The concept of custom phases is an advertised feature of UVM, if  we want to insert a phase called my_phase  we can do so by the concept of custom phases.

 Lets see how and where this  custom phase(s) i,e my_phase  can be inserted in the UVM phases with an example(coming soon).Would explore more on this and update this post 

Between take a look at an example  of  the UVM 1.2 phase introspection API @http://www.edaplayground.com/s/4/1085


-Happy Reading
Hash

Disclaimer: This is a small forum where i keep updating  learnt  from various online resources/People/attended training's and any due credit goes to them-the experts 

Friday 25 April 2014

Dear Readers

 Lets discuss some more things about the factory pattern -Where we use/don't use factory pattern in the UVM test bench

1)To run the test by registering with the factory 
     If you want to run any test i.e my_test it should be registered with the factory pattern 
  
2)for all the UVM  test bench components

     UVM test bench components like driver/monitor/scoreboard/sequencer

3)For all the objects in the UVM test bench 
4)Not for the static connections 

As Factory is used for dynamic interconnections we can not use factory pattern for interfaces, coverage,cover groups,TLM ports/FIFOs

-Happy Reading
Hash


Tuesday 15 April 2014

Dear Readers

Lets consider an  UVM TB (With a connected DUT)  with  the data(i.e the sequence items) flowing in and out of the DUT. This data  would be stored in the class based format which would be from uvm_sequence_item or uvm_sequence 

-Happy Reading
Hash

Monday 24 March 2014

Dear Readers

Found this  http://colorlesscube.com/uvm-guide-for-beginners/ really good to  get started on UVM along with Cluelogic.

 Hope you would find it useful

-Happy Reading
Hash

Tuesday 18 March 2014

Dear Readers,


One of our friends had some difficulty on "Testcase Parameters & Contents/Template of the test-case file"

Victor of Edaplayground.com has answered this query and due credit goes to Victor 

Lets understand how the  test case parameters can be driven inside the test bench environment  & the contents/template of the test case file?



In UVM, we typically use the uvm_config_db to parametrize the verification environment with methods like:
uvm_config_db#(string)::set
uvm_config_db#(string)::get

And +uvm_set_config_* options from the command line

References 


1)https://verificationacademy.com/verification-methodology-reference/uvm/docs_1.1d/html/files/base/uvm_cmdline_processor-svh.html#uvm_cmdline_processor.+uvm_set_config_int,+uvm_set_config_string

2)These  methods are used  in this UVM 1.2 example: 
http://www.edaplayground.com/s/4/1032


-Happy Reading
Hash

Wednesday 26 February 2014

Dear Readers

Lets write small piece of code to print UVM Library version number using Verilog.

2)You can also refer to

 http://www.dvteclipse.com/uvm-1.1-HTML_API/summary-macro-global.html
 http://www.edaplayground.com/x/4_y

-Happy Reading
Hash

**********************************************************************
module dummy_printer();
initial
begin
$display("*****************");
$display(`UVM_VERSION_STRING);
$display("******************");
end
endmodule

-- Compiling module dummy_printer

Top level modules:
dummy_printer
Reading /altera-quartus/13.1/modelsim_ase/tcl/vsim/pref.tcl 

# 10.1d

# vsim -do {onElabError resume; run -all; exit} -c -suppress 3829 -sv_lib uvm_dpi dummy_printer 
# Loading sv_std.std
# Loading work.dummy_printer
# onElabError resume 
# resume
#  run -all 
# *****************
# UVM-1.1d
# ******************
*********************************************************************************************

Thursday 13 February 2014

Dear Readers

Was going through UVM forums and came across this  "running a test" /tests per simulation",thought would add some more information and post it here.

Command line 

My_Simulator +UVM_TESTNAME=my_test1


Test:-

Lets understand about the test (my_test1 ) aka test scenario is a time consuming sequence in UVM ,could be a virtual sequence.An UVM test builds TB architecture , decides what sequence(s) are to be run ,end of test ,test pass/fail mechanism .There can be ONLY one test per simulation 

Lets understand "Test scenario can be possibly a virtual sequence".Let's assume the user has test1 that runs sequence1 and test2 that runs sequence2.

We  can create a higher level sequence (virtual sequence), and this sequence should start sequence1 and then start sequence2. Then  can have a single test that runs that virtual sequence.



This is  a case of sequence calling a sequence (nested sequences)?
b) If Yes, the test1 can be a single high level sequence(Virtual sequence) which can keep calling N sequences from within ?  This way , with a single test we can execute/cover all/most scenarios ?

Yes. There are several ways to do it.A sequence must run on a sequencer but it can be started by another sequence. A sequencer (virtual or not) is a structural uvm component which is created during build phase. A sequence (sequence_item) can be created any time.

So, in the original example, the virtual sequencer would have the handles to the original sequencer1 and sequencer2 for sequence1 and sequence2.. The virtual sequence can get those handles like: p_sequencer.sequencer1

-Happy Reading
Hash

Wednesday 12 February 2014

Dear Readers

I loved these articles on "Re-Usable sequences & Virtual sequences "  on VIP Central
Hope you also find these interesting 

http://www.vip-central.org/2012/11/reusable-sequences-in-uvm/
http://www.vip-central.org/2012/11/virtual-sequences-in-uvm-why-how/

-Happy Reading
Hash

Wednesday 22 January 2014

Dear Readers

 Take a look at video series introducing the features/changes in the upcoming UVM 1.2. 

  Victor Lyuboslavsky of edaplayground.com  put a post on Accellera forums
  I personally liked it as there is no dead code and no snapshots of code.

http://forums.accellera.org/topic/1671-uvm-12-introduction-and-code-examples/#entry6346

To know what has changed in UVM1.2 take a look at this  youtube video

http://www.youtube.com/embed/V2l4lBlsh7k?list=SPScWdLzHpkAdYPk_jgxRgOPisTm3-7U6A&vq=hd720

-Happy Reading
Hash

Dear Readers

There are 25 you tube videos on Basic UVM by Cadence and i found them useful  for my own learning,hope you also find them interesting!



http://www.youtube.com/playlist?list=PL7FE0CE1170C06FDE


2) There are 12 more YouTube videos on the overview of the concepts, components and applications of the UVM register layer as below

Introduction  http://www.youtube.com/watch?v=1tgjE4_XBek&feature=share&list=PLYdInKVfi0KZTCUqiD3hQweegKOwCzB7W


Testbench Integration
 http://www.youtube.com/watch?v=zjK5CgOHC3k&feature=share&list=PLYdInKVfi0KZTCUqiD3hQweegKOwCzB7W

Adapter
http://www.youtube.com/watch?v=hCB27zTUfqQ&feature=share&list=PLYdInKVfi0KZTCUqiD3hQweegKOwCzB7W

Predictor & Auto Predict
http://www.youtube.com/watch?v=hjpcd5nEbgc&feature=share&list=PLYdInKVfi0KZTCUqiD3hQweegKOwCzB7W


Register Model & Generation
http://www.youtube.com/watch?v=_z33XewYBko&feature=share&list=PLYdInKVfi0KZTCUqiD3hQweegKOwCzB7W


IP-XACT
http://www.youtube.com/watch?v=lnzg9fR0VW4&feature=share&list=PLYdInKVfi0KZTCUqiD3hQweegKOwCzB7W

Register Model Classes
http://www.youtube.com/watch?v=snEVMYp-qak&feature=share&list=PLYdInKVfi0KZTCUqiD3hQweegKOwCzB7W



Register API & Sequences
http://www.youtube.com/watch?v=rerF8SMKe2M&feature=share&list=PLYdInKVfi0KZTCUqiD3hQweegKOwCzB7W

Access Policies

http://www.youtube.com/watch?v=sRdxj25YGrI&feature=share&list=PLYdInKVfi0KZTCUqiD3hQweegKOwCzB7W

Frontdoor & Backdoor

http://www.youtube.com/watch?v=0WB_2N1qmPg&feature=share&list=PLYdInKVfi0KZTCUqiD3hQweegKOwCzB7W


Predefined Sequences

http://www.youtube.com/watch?v=OO3Y7gzjZoA&feature=share&list=PLYdInKVfi0KZTCUqiD3hQweegKOwCzB7W


Demonstration

http://www.youtube.com/watch?v=OHIxD9rRFL8&feature=share&list=PLYdInKVfi0KZTCUqiD3hQweegKOwCzB7W

-Best Wishes
Hash

Disclaimer  : Have JUST posted here as I find it interesting!

Friday 10 January 2014

Dear Readers

Lets talk again about the basic difference between Sequencers & Virtual Sequencers 

The basic difference between them is Virtual Sequencers are independent of protocol where as Sequencers are protocol /interface specific for that particular transaction

Thereby Virtual Sequencers control protocol /interface Sequencers and executes Virtual Sequences to control Protocol/Interface Sequences!

Hope you find it useful

-Happy Reading
Hash

Thursday 2 January 2014

Dear Readers

Best Wishes for a Happy & Wonderful New year.

Would schedule some effort to post more code,UVC's ,Advanced UVM in 2014.

Feel free to share your feedback/comments to make it better

-Happy Reading
Hash