Dear Readers

Lets write small piece of code to print UVM Library version number using Verilog.

2)You can also refer to

 http://www.dvteclipse.com/uvm-1.1-HTML_API/summary-macro-global.html
 http://www.edaplayground.com/x/4_y

-Happy Reading
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**********************************************************************
module dummy_printer();
initial
begin
$display("*****************");
$display(`UVM_VERSION_STRING);
$display("******************");
end
endmodule

-- Compiling module dummy_printer

Top level modules:
dummy_printer
Reading /altera-quartus/13.1/modelsim_ase/tcl/vsim/pref.tcl 

# 10.1d

# vsim -do {onElabError resume; run -all; exit} -c -suppress 3829 -sv_lib uvm_dpi dummy_printer 
# Loading sv_std.std
# Loading work.dummy_printer
# onElabError resume 
# resume
#  run -all 
# *****************
# UVM-1.1d
# ******************
*********************************************************************************************

Dear Readers

Was going through UVM forums and came across this  "running a test" /tests per simulation",thought would add some more information and post it here.

Command line 

My_Simulator +UVM_TESTNAME=my_test1


Test:-

Lets understand about the test (my_test1 ) aka test scenario is a time consuming sequence in UVM ,could be a virtual sequence.An UVM test builds TB architecture , decides what sequence(s) are to be run ,end of test ,test pass/fail mechanism .There can be ONLY one test per simulation 

Lets understand "Test scenario can be possibly a virtual sequence".Let's assume the user has test1 that runs sequence1 and test2 that runs sequence2.

We  can create a higher level sequence (virtual sequence), and this sequence should start sequence1 and then start sequence2. Then  can have a single test that runs that virtual sequence.



This is  a case of sequence calling a sequence (nested sequences)?
b) If Yes, the test1 can be a single high level sequence(Virtual sequence) which can keep calling N sequences from within ?  This way , with a single test we can execute/cover all/most scenarios ?

Yes. There are several ways to do it.A sequence must run on a sequencer but it can be started by another sequence. A sequencer (virtual or not) is a structural uvm component which is created during build phase. A sequence (sequence_item) can be created any time.

So, in the original example, the virtual sequencer would have the handles to the original sequencer1 and sequencer2 for sequence1 and sequence2.. The virtual sequence can get those handles like: p_sequencer.sequencer1

-Happy Reading
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Dear Readers

I loved these articles on "Re-Usable sequences & Virtual sequences "  on VIP Central
Hope you also find these interesting 

http://www.vip-central.org/2012/11/reusable-sequences-in-uvm/
http://www.vip-central.org/2012/11/virtual-sequences-in-uvm-why-how/

-Happy Reading
Hash