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Wednesday 21 May 2014

Dear Readers,


Lets talk about the concept of verbosity in UVM, UVM_LOW,UVM_HIGH,UVM_MEDIUM

Lets try to understand this with an example - Think of UVM_LOW/MEDIUM/HIGH as stones of various sizes and take a basic sand filter. If we set the filter size as low , the stone which are  bigger than the size of the filter would not be through .
I.e if the  filter is set to MEDIUM the stones which are LOW/MEDIUM would be through the filter and HIGH would not be there .If we set the filter is set to HIGH then we can see the LOW/MEDIUM/HIGH would be  through.


If we apply the same concept to UVM and set the verbosity as UVM_MEDIUM  in the log file we can see the messages UVM_LOW,UVM_MEDIUM  and UVM_HIGH would be filtered out
The same way if we set the verbosity to UVM_HIGH everything LOW/HIGH/MEDIUM would be present in the log file  JUST think the filter as simulation filter

-Happy Reading
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Sunday 11 May 2014

Dear Readers

While doing mock interviews this afternoon, came across this "what would be the difference between an object & component in UVM" ,thought of posting here



1) Objects are means of communication between components
2)Objects  can created and destroyed may times in over all simulation
3)Where as component are created only and once created they remain the same thou the simulation
4)Objects don't have phases and components have phases
5)Example of a component- all uvm components such as sequence item, sequencer.
6) Objects can be overridden and so can be the components by the factory
7) components have hierarchy and objects will not have hierarchy i.e the parent is agent is env, parent to env is test case


-Happy Reading
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Friday 9 May 2014

Dear Readers

 Found out these technical tutorials on UVM very interesting,take a look @ http://videos.accellera.org/uvmnownext/uvm349db45sh/index.html

Hope you find it good

-Happy Learning
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Dear Readers

 JUST posting a discussion  on "differences between UVM Transaction & an UVM object from Verification academy. As it is well answered in the forum  lets directly refer to the thread and let i find it  good  https://verificationacademy.com/forums/uvm/difference-between-uvm-transaction-and-uvm-object

Hope you find it useful

-Happy Reading
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Wednesday 7 May 2014

Dear Readers

One of our friends has a question about special ports( below) in UVM and how these ports are used in communication and what type of applications we may require this kind of ports.


uvm_blocking_put_imp_decl
uvm_blocking_master_imp_decl
`uvm_master_imp_decl etc...

As we know in UVM communication between the various components is by connecting ports to the suitable exports .

These special ports (above) are different variations of TLM API and can find more about these special ports on https://verificationacademy.com/verification-methodology-reference/uvm/docs_1.1d/html/files/tlm1/uvm_tlm_ifs-svh.html


Due credit goes to Victor Lyuboslavsky for answering this 

-Happy Reading
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Dear Readers

 One of our friends has a question on Custom Phases of UVM. Would try to post as much information (i have) on this and would keep updating this post.

As we all know that UVM phases build,connect, end of elaboration, start of simulation,run, extract, check and report.

 The concept of custom phases is an advertised feature of UVM, if  we want to insert a phase called my_phase  we can do so by the concept of custom phases.

 Lets see how and where this  custom phase(s) i,e my_phase  can be inserted in the UVM phases with an example(coming soon).Would explore more on this and update this post 

Between take a look at an example  of  the UVM 1.2 phase introspection API @http://www.edaplayground.com/s/4/1085


-Happy Reading
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Disclaimer: This is a small forum where i keep updating  learnt  from various online resources/People/attended training's and any due credit goes to them-the experts