Dear Readers

I found this Youtube Video - UVM by Mentor real good and easier to learn.
Hope you would find this interesting!


http://www.youtube.com/watch?v=kA7jiowZq3w

 -Happy Reading
Hash

Dear Readers

Let us take a look at coding the following things one step at a time in a series of steps
Initially we would understand the basic template, populate the list of files (in step-1) with an example 


-Happy Reading
Hash

Step1) List of files

Sequence item                                     i.e my_simple_sequence_item.sv
Sequencer                                            i.e my_simple_sequencer.sv
Driver                                                   i.e my_simple_driver.sv
Env                                                       i.e my_simple_env.sv     
How to run the test                            i.e my_simple_program.sv


Step2)Templates 

 Lets take a look at the default templates for each of the above files 

a)my_simple_sequence_item.sv

  What does this my_simple_sequence_item  contain- This would contain all signals ,constraints, transfers

 a)Include  uvm macros
 b)As UVM is made of classes & libraries ,lets declare class my_simple_sequence_item which would be extended from uvm_sequence_item

********************************************************************************
//Include uvm macros
  import uvm_pkg::*;
 `include "uvm_macros.svh"
// Code begin line #1
 class my_simple_sequence_item extends uvm_sequence_item;

//Factory registration
//Boiler plate code start
//Boiler plate code end
//Signals declaration
//constraints 
 //Code end   
endclass : my_simple_sequence_item
*********************************************************************************

Step-3)Codes

a)my_simple_sequence_item.sv

********************************************************************************
//Include uvm macros
  import uvm_pkg::*;
 `include "uvm_macros.svh"
// Code begin line #1
 class my_simple_sequence_item extends uvm_sequence_item;
rand bit [3:0] a,b;
rand bit [31:0] c[];
constraint valid {c.size inside {[2:50]};}
`uvm_object_utils_begin(my_simple_sequence_item)
`uvm_field_int(a,UVM_ALL_ON)
`uvm_field_int(b,UVM_ALL_ON)
`uvm_field_array_int(c,UVM_ALL_ON)
`uvm_object_utils_end
function new(string name = "my_simple_sequence_items");
super.new(name);
endfunction
//Factory registration
//Boiler plate code start
//Boiler plate code end
//Signals declaration
//constraints 
 //Code end   
endclass : my_simple_sequence_item
*********************************************************************************

b)my_simple_sequencer.sv

*********************************************************************************

//`include "uvm_macros.svh"
import uvm_pkg::*;
 class my_simple_sequencer extends uvm_sequencer #(my_simple_sequence_item);
`uvm_sequencer_utils(my_simple_sequencer)
function new(string name,uvm_component parent);
super.new(name,parent);
`uvm_update_sequence_lib_and_item(my_simple_sequence_item)
endfunction
endclass

*********************************************************************************

c)my_simple_driver.sv

********************************************************************************
  import uvm_pkg::*;
`include "uvm_macros.svh"
class my_simple_driver extends uvm_driver #(my_simple_sequence_item);
`uvm_component_utils(my_simple_driver)
function new(string name,uvm_component parent);
super.new(name,parent);
endfunction
virtual task run();
forever begin
seq_item_port.get_next_item(req); 
uvm_report_info("Normal" , "This is a simple_driver item");
req.print();
seq_item_port.item_done();
end
endtask
endclass

********************************************************************************

d)my_simple_env.sv

********************************************************************************
import uvm_pkg::*;
`include "uvm_macros.svh"
class my_simple_env extends uvm_component;
my_simple_sequencer sequencer;
my_simple_driver    driver;
`uvm_component_utils_begin(my_simple_env)
`uvm_field_object(sequencer,UVM_DEFAULT)
`uvm_field_object(driver,UVM_DEFAULT);
`uvm_component_utils_end

function new(string name,uvm_component parent);
super.new(name,parent);
endfunction
virtual function void build();
super.build();
sequencer = new("sequencer", this);
driver    = new("driver",this);
endfunction
virtual function void connect();
super.connect();
driver.seq_item_port.connect(sequencer.seq_item_export);
endfunction
endclass

*********************************************************************************

e)my_simple_program.sv

********************************************************************************

`include "my_simple_sequence_item.sv" 

`include "my_simple_sequencer.sv" 

`include "my_simple_driver.sv"

`include "my_simple_env.sv"

program dummy_progrm;

 //Import the uvm_package

 import uvm_pkg::*;

`include "uvm_macros.svh"

class my_test extends uvm_component;

//Factory registration

`uvm_component_utils(my_test)

my_simple_env env;   

//Boiler plate code start

function new (string name,uvm_component parent);

super.new(name,parent);

endfunction

function void build();

env=my_simple_env::type_id::create("env",this);

endfunction

//Boiler plate code end 

virtual task run();

uvm_test_done.raise_objection(this);

uvm_report_info("Message","my_test");

 uvm_top.print_topology();

uvm_test_done.drop_objection(this);

global_stop_request();

//Print what all types are available in the factory

    factory.print();

    //Print the TB structure

   uvm_top.print_topology();

endtask

//standard phase methods

endclass

initial   begin

uvm_default_printer = uvm_default_tree_printer;

fork

    run_test("my_test");

#500 global_stop_request();

join

 uvm_top.print_topology();

      end

endprogram

*********************************************************************************


f)Log

*********************************************************************************
# ----------------------------------------------------------------
# UVM-1.1b
# (C) 2007-2012 Mentor Graphics Corporation
# (C) 2007-2012 Cadence Design Systems, Inc.
# (C) 2006-2012 Synopsys, Inc.
# (C) 2011-2012 Cypress Semiconductor Corp.
# ----------------------------------------------------------------
# 
#   ***********       IMPORTANT RELEASE NOTES         ************
# 
#   You are using a version of the UVM library that has been compiled
#   with `UVM_NO_DEPRECATED undefined.
#   See http://www.eda.org/svdb/view.php?id=3313 for more details.
# 
#   You are using a version of the UVM library that has been compiled
#   with `UVM_OBJECT_MUST_HAVE_CONSTRUCTOR undefined.
#   See http://www.eda.org/svdb/view.php?id=3770 for more details.
# 
#       (Specify +UVM_NO_RELNOTES to turn off this notice)
# 
# UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(215) @ 0: reporter [Questa UVM] QUESTA_UVM-1.2
# UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(217) @ 0: reporter [Questa UVM]  questa_uvm::init(+struct)
# UVM_INFO @ 0: reporter [RNTST] Running test my_test...
# UVM_WARNING verilog_src/uvm-1.1b/src/seq/uvm_sequencer_base.svh(1436) @ 0: uvm_test_top.env.sequencer [UVM_DEPRECATED] Registering sequence 'uvm_random_sequence' with sequencer 'uvm_test_top.env.sequencer' is deprecated. 
# UVM_WARNING verilog_src/uvm-1.1b/src/seq/uvm_sequencer_base.svh(1436) @ 0: uvm_test_top.env.sequencer [UVM_DEPRECATED] Registering sequence 'uvm_exhaustive_sequence' with sequencer 'uvm_test_top.env.sequencer' is deprecated. 
# UVM_WARNING verilog_src/uvm-1.1b/src/seq/uvm_sequencer_base.svh(1436) @ 0: uvm_test_top.env.sequencer [UVM_DEPRECATED] Registering sequence 'uvm_simple_sequence' with sequencer 'uvm_test_top.env.sequencer' is deprecated. 
# UVM_INFO @ 0: uvm_test_top [Message] my_test
# ......................///////////////////////////////////////////////////////
# UVM_INFO @ 0: reporter [UVMTOP] UVM testbench topology:
# uvm_test_top: (my_test@503) {
#   env: (my_simple_env@511) {
#     driver: (my_simple_driver@643) {
#       rsp_port: (uvm_analysis_port@660) @660 
#       sqr_pull_port: (uvm_seq_item_pull_port@651) @651 
#     }
#     sequencer: (my_simple_sequencer@520) {
#       rsp_export: (uvm_analysis_export@528) @528 
#       seq_item_export: (uvm_seq_item_pull_imp@634) @634 
#       arbitration_queue: - 
#       lock_queue: - 
#       num_last_reqs: 'd1 
#       num_last_rsps: 'd1 
#     }
#     sequencer: (my_simple_sequencer@520) {
#       rsp_export: (uvm_analysis_export@528) @528 
#       seq_item_export: (uvm_seq_item_pull_imp@634) @634 
#       arbitration_queue: - 
#       lock_queue: - 
#       num_last_reqs: 'd1 
#       num_last_rsps: 'd1 
#     }
#     driver: (my_simple_driver@643) {
#       rsp_port: (uvm_analysis_port@660) @660 
#       sqr_pull_port: (uvm_seq_item_pull_port@651) @651 
#     }
#   }
# }
# 
# 
#### Factory Configuration (*)
# 
# Instance Overrides:
# 
#   Requested Type     Override Path                     Override Type          
#   -----------------  --------------------------------  -----------------------
#   uvm_sequence_item  uvm_test_top.env.sequencer*.item  my_simple_sequence_item
# 
# No type overrides are registered with this factory
# 
# All types registered with the factory: 43 total
# (types without type names will not be printed)
# 
#   Type Name
#   ---------
#   my_simple_driver
#   my_simple_env
#   my_simple_sequence_item
#   my_simple_sequencer
#   my_test
#   questa_uvm_recorder
# (*) Types with no associated type name will be printed as <unknown>
# 
####
# 
# UVM_INFO @ 0: reporter [UVMTOP] UVM testbench topology:
# uvm_test_top: (my_test@503) {
#   env: (my_simple_env@511) {
#     driver: (my_simple_driver@643) {
#       rsp_port: (uvm_analysis_port@660) @660 
#       sqr_pull_port: (uvm_seq_item_pull_port@651) @651 
#     }
#     sequencer: (my_simple_sequencer@520) {
#       rsp_export: (uvm_analysis_export@528) @528 
#       seq_item_export: (uvm_seq_item_pull_imp@634) @634 
#       arbitration_queue: - 
#       lock_queue: - 
#       num_last_reqs: 'd1 
#       num_last_rsps: 'd1 
#     }
#     sequencer: (my_simple_sequencer@520) {
#       rsp_export: (uvm_analysis_export@528) @528 
#       seq_item_export: (uvm_seq_item_pull_imp@634) @634 
#       arbitration_queue: - 
#       lock_queue: - 
#       num_last_reqs: 'd1 
#       num_last_rsps: 'd1 
#     }
#     driver: (my_simple_driver@643) {
#       rsp_port: (uvm_analysis_port@660) @660 
#       sqr_pull_port: (uvm_seq_item_pull_port@651) @651 
#     }
#   }
# }
# 
# UVM_INFO verilog_src/uvm-1.1b/src/base/uvm_objection.svh(1120) @ 0: reporter [TEST_DONE] 'run' phase is ready to proceed to the 'extract' phase
# 
# --- UVM Report Summary ---
# 
# ** Report counts by severity
# UVM_INFO :    7
# UVM_WARNING :    3
# UVM_ERROR :    0
# UVM_FATAL :    0
# ** Report counts by id
# [Message]     1
# [Questa UVM]     2
# [RNTST]     1
# [TEST_DONE]     1
# [UVMTOP]     2
# [UVM_DEPRECATED]     3
# ** Note: $finish    : C:/modeltech64_10.1c/win64/../verilog_src/uvm-1.1b/src/base/uvm_root.svh(408)

#    Time: 0 ns  Iteration: 184  Instance: /dummy_progrm
*********************************************************************************

Disclaimer : This is just a small effort to learn UVM and all  feedback is welcome

Dear Readers


Let us get started on how to build a UVM testbench given a DUT and timing diagrams in  a series of steps.
Take a dummy DUT as below.

Step-1

Lets  discuss the various components of a UVM testbench

  1)Sequencer              Class 
  2)Driver                    Class
  3)Scoreboard           Class
  4)Ports
  5)Virtual Interface
  6)Top Level module
  7)Interface
  8)Analysis Port
  9)Environment 

Step-2 

 Lets map all the components above in step-1 to UVM 
UVM testbench with all the mentioned components(Block diagram coming up)


Step-3

Lets look at a dummy DUT Pint out (Coming up soon)

Step-4 

Lets  have the timing diagrams for the dummy DUT (Coming up soon)

Step-5


Once we have a dummy DUT,timing diagrams and lets see how to build a UVM testbench 

Step-6

Lets list down the required files for the UVM testbench  as below

 1)Sequencer        i.e my_sequencer.sv                  (Class based)  
  2)Driver              i.e my_driver.sv                        (Class based)
  3)Scoreboard     i.e my_scoreboard.sv                (Class based)
  4)Top  module    i.e my_top.sv 
  5)Interface          i.e my_interface.sv
  6)Environment     i.e  my_env.sv
 7)Monitor            i.e my_monitor.sv  
   8)Sequence        i.e  my_sequence.sv
    9)Test               i.e my_test.sv       
  10)Agent            i.e  my_agent.sv
 11)Seq item         i.e  my_seq_item.sv
12)Config db        i.e  my_config_db.sv

Step-7

 Lets populate the codes for the files in step-6(Coming up soon)


-Happy Reading
Hash
    

Disclaimer

This is JUST to  give a basic understanding in terms of -Look & feel of UVM testbench-Various components-what all files we need to create for a UVM testbench and how to populate the files to get started. Its a small effort to create an UVM testbench given a DUT and timing diagram and the codes MAY NOT BE CLEAN COMPILE at the moment.

Dear Readers,

 Let us start looking at more UVM code examples going forward 

Let us print the  customary  "Hello World" example as the first step in learning UVM 
Use the same things which we used in Verilog programming

Please refer to the steps-1,2.. and the highlighted messages(in Blue)

-Happy Reading
Hash

//Step-1Take any dummymodule 
module dummy_helloworld;
//Step-2 Include the UVM Macros 
//If we dont include the UVM Macros the tool could not recognise
//the uvm_report_info and throws out an error message as below
//As UVM is a class based library and including the libraries for printing 
//uvm_report info would fix the issue
// Invalid argument. (errno = EINVAL)
// ** Error: F:/Hash/dummy_helloworld.sv(7): Failed to find 'uvm_report_info' in hierarchical name /uvm_report_info.
// Optimization failed
 import uvm_pkg::*;
initial
 begin
//Step-3 Print what you want
//Instead of our $display in Verilog we should use //uvm_report_info/warning/error/fatal 
//As this is just a message use "info",to display the string we wanted
//The main difference is this uvm_report_info/warning/error/fatal is it should be minimum //of  2 fields and a max of 5 fields
//Step-4Lets print  the strings "DUMMY_TEST" & "Hello World"  on the log file
 uvm_report_info("DUMMY_TEST","Hello_World");
 end
endmodule

*********************************************************************************
 QuestaSim vlog 10.0b Compiler 2011.05 May  5 2011
# -- Compiling module dummy_helloworld
# -- Importing package mtiUvm.uvm_pkg (uvm-1.0p1 Built-in)
# Top level modules:
# Loading sv_std.std
# Loading mtiUvm.uvm_pkg
# Loading work.dummy_helloworld(fast)
# Loading C:\questa_sim_10.0b\uvm-1.0p1\win32\uvm_dpi.dll
run
# ----------------------------------------------------------------
# UVM-1.0p1 
# (C) 2007-2011 Mentor Graphics Corporation
# (C) 2007-2011 Cadence Design Systems, Inc.
# (C) 2006-2011 Synopsys, Inc.
# ----------------------------------------------------------------
# UVM_INFO @ 0: reporter [DUMMY_TEST] Hello_World
********************************************************************************

Dear Readers

Lets take a look at a simple  objection mechanism which can be used to control the end of test
We are using the same template which is used for the first program "Hello world" to keep it simple 

-Happy Reading
Hash

*********************************************************************************
 program dummy_progrm;
 //Import the uvm_package
 import uvm_pkg::*;
`include "uvm_macros.svh"
class hello_world extends uvm_component;
//Factory registration
`uvm_component_utils(hello_world)
//Boiler plate code start
function new (string name,uvm_component parent);
super.new(name,parent);
endfunction
//Boiler plate code end 
virtual task run();
uvm_test_done.raise_objection(this);
uvm_report_info("Message","Hello World");
uvm_test_done.drop_objection(this);
global_stop_request();
//Print what all types are available in the factory
    factory.print();
    //Print the TB structure
   uvm_top.print_topology();
endtask
//standard phase methods
endclass
initial 
  begin
    run_test("hello_world");
      end
endprogram
*********************************************************************************

# Loading sv_std.std
# Loading mtiUvm.uvm_pkg
# Loading work.dummy_progrm(fast)
# Loading C:\questa_sim_10.0b\uvm-1.0p1\win32\uvm_dpi.dll
run
# ----------------------------------------------------------------
# UVM-1.0p1 
# (C) 2007-2011 Mentor Graphics Corporation
# (C) 2007-2011 Cadence Design Systems, Inc.
# (C) 2006-2011 Synopsys, Inc.
# ----------------------------------------------------------------
# UVM_INFO @ 0: reporter [RNTST] Running test hello_world...
# UVM_INFO @ 0: uvm_test_top [Message] Hello World
# 
#### Factory Configuration (*)
# 
#   No instance or type overrides are registered with this factory
# 
# All types registered with the factory: 37 total
# (types without type names will not be printed)
# 
#   Type Name
#   ---------
#   hello_world
# (*) Types with no associated type name will be printed as <unknown>
# 
####
# 
# UVM_INFO @ 0: reporter [UVMTOP] UVM testbench topology:
# --------------------------------------
# Name          Type         Size  Value
# --------------------------------------
# uvm_test_top  hello_world  -     @455 
# --------------------------------------
# 
# UVM_INFO verilog_src/uvm-1.0p1/src/base/uvm_objection.svh(1116) @ 0: reporter [TEST_DONE] 'run' phase is ready to proceed to the 'extract' phase
# 
# --- UVM Report Summary ---
# 
# ** Report counts by severity
# UVM_INFO :    4
# UVM_WARNING :    0
# UVM_ERROR :    0
# UVM_FATAL :    0
# ** Report counts by id
# [Message]     1
# [RNTST]     1
# [TEST_DONE]     1
# [UVMTOP]     1
# ** Note: $finish    : C:/questa_sim_10.0b/win32/../verilog_src/uvm-1.0p1/src/base/uvm_root.svh(392)
#    Time: 0 ns  Iteration: 187  Instance: /dummy_progrm
# 1
# Break at C:/questa_sim_10.0b/win32/../verilog_src/uvm-1.0p1/src/base/uvm_root.svh line 392

Dear Readers

Lets discuss some more things about UVM agent.

• Agents can be either active or passive
• Agents provide all Verification logic for a DUT
• An active agent is driven on an interface/device with all Sequencer/driver/Monitor being available
• A passive agent has ONLY monitor available -Can do  checking & collect  coverage  
• Any Bus protocol can have N no of devices each of which is represented as an agent 
• An env has multiple agents which encapsulates and configures multiple agents, which is also known as UVC-Universal Verification component 
• Encapsulation this UVCs makes it modular and easy to maintain and Virtual sequences enable control at System Level

Happy Reading

Hash

Dear Readers

Lets see how we can customize the factory and how you construct the agents
For constructing the agents we should use the create method,create checks for the factory over ride and constructs for the objects accordingly.

From the previous post lets get started without getting into if agent is active/passive, the sample code as below. 

******************************************************************************

class my_agent extends uvm_agent;
//Factory registration
// Using uvm_component_utils as agent is a TB component 
`uvm_component_utils(my_agent)
//External interfaces
virtual dut_if dut_ifs;
//Internal interfaces 
       monitor mon;
        driver drv;
//Boiler plate code start

     function new(string name, uvm_component parent);
         super.new(name, parent);
     endfunction
//Boiler plate code end
//Standard phase methods
function void build();
super.build();
//As the agent contains sequencer, driver, monitor we can construct the agent as below
uvm_report_info(get_full_name(),"Build", UVM_LOW);
//Customization using the factory
 my_seq_1  = my_seq ::type_id::create("my_seq_1", this);  
 my_driv_1 = my_driv::type_id::create("my_driv_1", this);   
my_mon_1  = my_mon ::type_id::create("my_mon_1", this);
 endfunction: build 

//Other Standard phase methods

     function void connect();

         uvm_report_info(get_full_name(),"Connect", UVM_LOW);

     endfunction

     function void end_of_elaboration();

         uvm_report_info(get_full_name(),"End_of_elaboration", UVM_LOW);

     endfunction

     function void start_of_simulation();

         uvm_report_info(get_full_name(),"Start_of_simulation", UVM_LOW);

     endfunction

     task run();

         uvm_report_info(get_full_name(),"Run", UVM_LOW);

     endtask

     function void extract();

         uvm_report_info(get_full_name(),"Extract", UVM_LOW);

     endfunction

     function void check();

         uvm_report_info(get_full_name(),"Check", UVM_LOW);

     endfunction

     function void report();

         uvm_report_info(get_full_name(),"Report", UVM_LOW);

     endfunction

endclass
*********************************************************************************

-Happy Reading
Hash

Dear Readers

Please feel free to email me and all suggestions/feedback is welcome to make this small effort better.

Lets examine the basic structure of a UVM component and see how it looks like ,hope you find it useful.

The basic building items of a UVM component are as follows bounded between class, endclass keywords as below


class my_component extends uvm_component


1)factory registration
2)external interfaces
3)Internal component handles
4)Boiler plate code
5)Standard phase methods (which we have discussed in the previous blog)

endcomponent 

Let us discuss at these things one by one, this is NOT a clean compile example but can be used for writing UVM TB components

********************************************************************************

class my_component extends uvm_component;

// We need to use uvm_component_utils as uvm_object_utils is NOT used for 
//TB components .uvm_object_utils is used in stimulus generation part
//Factory registration 
`uvm_component_utils(my_component)
//external interfaces
virtual dut_if dut_ifs;
//Internal component handles
        monitor mon;
        driver drv;
//Boiler plate code start
//Boiler plate code which is mandatory for all UVM TB components
 function new(string name, uvm_component parent);
         super.new(name, parent);
//Boiler plate code end 
     endfunction

//Standard Phase methods
 function void build();
         uvm_report_info(get_full_name(),"Build", UVM_LOW);
            endfunction

     function void connect();
         uvm_report_info(get_full_name(),"Connect", UVM_LOW);
     endfunction

     function void end_of_elaboration();
         uvm_report_info(get_full_name(),"End_of_elaboration", UVM_LOW);
     endfunction

     function void start_of_simulation();
         uvm_report_info(get_full_name(),"Start_of_simulation", UVM_LOW);
     endfunction

     task run();
         uvm_report_info(get_full_name(),"Run", UVM_LOW);
     endtask

     function void extract();
         uvm_report_info(get_full_name(),"Extract", UVM_LOW);
     endfunction

     function void check();
         uvm_report_info(get_full_name(),"Check", UVM_LOW);
     endfunction

     function void report();
         uvm_report_info(get_full_name(),"Report", UVM_LOW);
     endfunction

endclass
*********************************************************************************

-Happy Reading
Hash

Dear Readers

First let me Wish you all Happy festive days
Please feel free to email me with your suggestions/feedback and i am open for any constructive ideas which makes this small effort get better

We all know that UVM has the following simulation phase methods-Build time,run time & clean up 

UVM Simulation phase methods can be classified as build,connect, end of elaboration, start of simulation, run and clean up phases(extract, check,report)

Build ,connect, end of elaboration ,start of simulation, run, extract, check,report ,Final

Out of these phases ONLY build is the top down method and all others are bottom up methods ,all phase methods except RUN are functions and RUN is a  task.

So lets see what actually happens in each and every simulation phase method here 

During the build phase the factory is called and used to Construct various child components/ ports/exports and configured,the top level testbench topology is built 

During the connect phase the TLM connections are made and the ports/exports of the components are Connected. i.e, the environment topology is connected.

During the end of elaboration the connections are checked and used for configuring the components. Post elaboration activity and the topology is printed 

During the start of simulation the various files are opened  banner information /topology would be being printed (as below)

# ----------------------------------------------------------------

# UVM-1.0p1 

# (C) 2007-2011 Mentor Graphics Corporation

# (C) 2007-2011 Cadence Design Systems, Inc.

# (C) 2006-2011 Synopsys, Inc.

# ----------------------------------------------------------------

During the run phase main test is executed and simulation is run
UVM adds 12 new phases which would be executed in parallel  with run_phase
These 12 new phases would be used to control stimulus which is explained as below

pre_reset,
reset
post_reset
pre_config
config
post_config
pre_main
main
post_main
pre_shutdown
shutdown
post_shutdown

The stimulus control being done by the objection mechanism, lets see the codes

class my_test_phase extends uvm_test_phase;
//Factory registration
//Use component utils macro as its TB component
`uvm_component_utils(my_phase_test)
//Boiler Plate code which is mandatory for all UVM TB components
function new(string name ,uvm_component_parent)
super.new(name,parent);
//Boiler plate code end
endfunction

task ..._phase(uvm_phase phase)
phase.raise_objection(this, "Starting Phase");
//Sequence start
//end Sequence
phase.drop_objection(this, "Finished Phase");
endtask

endclass


Drivers and monitors would be using JUST this run_phase

During the extract, check, report,Final phase methods post processing is done and the required information /details are gathered on the final state of the DUT,results are checked for the extracted information and the test pass/fail reporting would be done.

One of the differences  between OVM and UVM is that there is no final phase method in ovm.

-Happy Reading
Hash

Dear Readers

Thought would post why the analysis port always uses new and NOT create?

The analysis port always uses  the same type of object and as it is not  a component and  does  not belong to the  factory hierarchy.

Ports are interfaces which  are not extending from either object or component, so we cannot use create and have to use new

-Happy Reading
Hash

Dear Readers

 I also found this very interesting, hope you enjoy reading it


http://www.dvteclipse.com/uvm-1.1-HTML_API/uvm_pkg-uvm_test.html#constructor

Happy Reading
Hash

Dear Readers

I was trying to understand where  polymorphism is used in UVM and i found this blogspot really interesting and its explained in detail with code examples

http://learn-verification.blogspot.in/2012/12/uvm-questions-3.html

Hope you also find it useful 

-Happy Reading
Hash