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Sunday 22 September 2013

Dear Readers

I had a doubt on the uvm_do & uvm_do_with macros and this is what i understand from the UVM discussion forums and posting here as it may be useful for the interviews 

 uvm_do and uvm_do_with macros, the answer is that the second one assumes you need to further constrain your sequence/sequence_item(by providing this constraint as the second macro parameter) before it is get consumed. 

uvm_do does the following  3 things, 
1) create object 
2) object.randomize 
3) send packet 


 uvm_do_with there is only one difference, it calls 'randomize with ' (inline constraints) instead of randomize.

Hope you find it useful

-Happy Reading
Hash

Disclaimer

Posting on this blog to learn building UVM test benches, UVCs ,UVM VIPs from various online sources/discussion forums/Attended  training/Seminars /Webinars/Interviews. Am JUST sharing here to Learn from the experts and make this small effort better as i believe learning is a continuous process. Due credit goes to the trainers/online resources 
Dear Readers

Came across this You tube video and found it real interesting.
This explains how to setup a UVM TB right from the scratch given a DUT pin diagram
http://www.youtube.com/watch?v=kA7jiowZq3w



Hope you find it useful,coming up next is "to create a UVM TB given a DUT Pin out and timing diagrams"


-Happy Reading
Hash

Disclaimer

Posting on this blog to learn building UVM test benches, UVCs ,UVM VIPs from various online sources/discussion forums/Attended  training/Seminars /Webinars/Interviews. Am JUST sharing here to Learn from the experts and make this small effort better as i believe learning is a continuous process. Due credit goes to the trainers/online resources 

Tuesday 17 September 2013

Dear Readers,

Came across this interesting topic on UVM discussion forums on linked in and posting on the blog as I found it real interesting! I JUST tried to organize the discussion to understand easily.

-Happy Reading
Hash


Topic: What are uvm_component_utils /uvm_object_utils and when to use these macros in UVM TB

As we all know that these uvm_component_utils /uvm_object_utils are the defined macros in UVM
There is a fundamental difference between objects and Components though both are classes that can be dynamically created while. Uvm_component is derived from uvm_object, and it adds the following:

1) Hierarchy management
2) Phasing
3) Reporting
4) configuration support
among other things.

Uvm_component -Should be used for objects that are of a "static" nature for the duration of the simulation
Uvm_object   should be used for other dynamically generated data, 

These macros are used for registering the type of uvm_component and uvm_object type objects respectively to the factory. So when you declare a class which is inherited from uvm_component, use uvm_component_utils and when you declare class inherited from uvm_object, use uvm_object_utils. 


They define uvm_component_registry and uvm_object_registry type proxy objects to register your own component/object types with factory. They are different because mechanism for creation of uvm_object and uvm_component type objects using the factory is different in UVM.


When to use uvm_component_utils /uvm_object_utils

On which factor the decision of using "uvm_component" or/either "uvm_object" depends.
 For eg. While creating "sequence" we use "uvm_seq_item" as base class & in this class we use "uvm_object_utils". Now let’s say in this case, if we use "uvm_component_utils" then what will be its impact.


Using either is not a choice, it’s more a must. One should have UVM class library hierarchy opened somewhere on the computer to see the type of the base class. If it is component then use uvm_component_utils, if object use the other one.


Use `uvm_component_utils for anything that is part of the UVM TB structure, including the top-level test that builds the rest of the TB.
Use `uvm_object_utils for anything that is data, such as your transaction class (extended from uvm_sequence_item) and any test sequences (extended from uvm_sequence).
You will not notice a difference until you try to create the components during the build phase or the data items during the runphase.
 If you declared the components or data with the wrong `_utils macro, you will get messages about the wrong number of formals or that there is no parent formal. Components have parents in the TB tree-structure while data is created as needed and does not have a parent. 

When we  build TB components i.e  Driver, Sequencer, Monitor, Agents, scoreboards , need to use uvm_component to register them, UVM provides individual parent classes for each of the components with in-built methods. so we just need to extend the class and build our  own components. 

UVM_objects is used for the things which are not part of the  TB structure i.e the stimulus. sequences use object, more clearly UVM_sequence and transaction class use UVM_Sequence items both directly derived from UVM_object. To keep the TB separate from the stimulus so that a test writer can alter its stimulus however he wanted a and the TB architecture remains unchanged. so it promotes more re-usability for the  TB


Disclaimer

Posting on this blog to learn building UVM test benches, UVCs ,UVM VIPs from various online sources/discussion forums/Attended  training/Seminars /Webinars/Interviews. Am JUST sharing here to Learn from the experts and make this small effort better as i believe learning is a continuous process. Due credit goes to the trainers/online resources 


Thursday 12 September 2013

Dear Readers

 Came across this UVM blog post and can not resist to  add to the good links list
http://art-of-verification.blogspot.in/
http://www.agilesoc.com/2013/09/09/uvm-boat-anchor-sneak-peek/

 Hope you find this useful

-Happy Reading
Hash



Wednesday 11 September 2013

Dear Readers

Posting some more information which would be useful in creating a UVM test bench given any given DUT
We would see on how to build UVM T/B with the steps below very soon.
Hope you find this useful and feel free to share your comments!

-Happy Reading
Hash

Steps to build UVM T/B given any DUT:

1. Read the design

   - List down features
   - List down scenarios
   - Create test plan

2. Understanding DUT architecture

  - List down DUT interfaces
      o What kind of interface is it: ACTIVE or PASSIVE?
      o Active will require Driver and Scenario generator

3. Test bench architecture

 This would have the following components

  - DUT instantiated
  - All interfaces defined
  - UVC components instantiated (agents for each interface, ex: axi_master_agent or axi_slave_agent, etc)
  - Reference model mimicking the Design behaviour
  - Register layer model
  - Virtual sequencer which will instantiate all sequencers
  - Virtual sequences which will instantiate required sequences from different interfaces

4. Sequences

  They will be coded specific to each interface
  - Simple sequences like, write, read sequences
  - Sequences for configuring design registers

5. Test Library
  - Test case coded using virtual sequence

Disclaimer

   Posting on this blog to learn building UVM test benches, UVCs ,UVM VIPs from various online sources/Attended  training/Seminars /Webinars. Am JUST sharing here to Learn from the experts and make this small effort better as i believe learning is a continuous process. Due credit goes to the trainers/online resources.