Dear Readers

Planning to write code for a clean compile UVC , stay tuned

2) More on TLM ,UVM Connect


-Happy Reading
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Dear Readers,

 protocol verification -some thoughts

For any protocol verification we can always generate a UVM TB
Lets see what all  minimum TB components  we should have - a  monitor  & interface signals for DUT Pins

A scoreboard is good if we want/need to  track the history/state of the protocol.
 A driver is only needed when the TB is ACTIVE -- if we  need to send responses on the bus or to create traffic.

Scenario-1

Lets think of a scenario  of no DUT & ONLY  "interface" for the pins of the DUT.
Is it possible to simulate UVM components without DUT?

 Yes.It is even possible to simulate your UVM components without the DUT. 

Please use the SV Unit framework to simulate a UVM driver:  

take a look http://www.edaplayground.com/s/example/205

-Happy Reading
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Dear Readers

Came across this interesting web while looking for sometime,find some time to take a look
Those who do not have access to a simulator but want to write test benches in UVM would fnd it real useful.

All you need to do is write  the design and T/B in your favorite text editor and copy it here in your free time or you can also write can code the design & TB here 

We can ONLY compile but cant simulate on this public version of EDA playground. we can simulate regular Verilog,OVL,MyHDL ,cocotb

http://www.edaplayground.com

-Happy Reading
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