Sunday, 24 November 2013

Dear Readers

Came across this interesting web while looking for sometime,find some time to take a look

Those who do not have access to a simulator but want to write test benches in UVM would fnd it real useful.

All you need to do is write  the design and T/B in your favorite text editor and copy it here in your free time or you can also write can code the design & TB here 

We can ONLY compile but cant simulate on this public version of EDA playground. we can simulate regular Verilog,OVL,MyHDL ,cocotb

-Happy Reading


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